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Proceedings of the 2001 international workshop on System-level interconnect prediction
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Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Reliability challenges for 45nm and beyond
Proceedings of the 43rd annual Design Automation Conference
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Proceedings of the 17th ACM Great Lakes symposium on VLSI
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Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
TROY: track router with yield-driven wire planning
Proceedings of the 44th annual Design Automation Conference
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Proceedings of the 44th annual Design Automation Conference
Post-routing redundant via insertion with wire spreading capability
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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This paper accurately considers wire short defects and proposes an algorithm to guarantee IC chip yield rate improvement for redundant wire insertion. Without considering yield rate degradation caused by shorts, traditional methods may even lead to yield rate loss. However, shorts are more complicated to analyze than opens. Moreover, since any two points of a routed net can be connected by a redundant wire, the number of possible insertion patterns for a chip is un-tractable. To maximize yield rate improvement and to make the problem tractable, we identify a key insight, tolerance-ratio, as an effective guide for choosing insertion patterns and insertion order. Finally, to guarantee yield rate improvement, only positive gain redundant wires are committed. Experimental results show that, compared with unprocessed cases, all yield rate improvements in the proposed algorithm are positive, and the defect rates are reduced by up to 65% and by 24% on average. On the other hand, without considering shorts, the defect rate can increase as much as 7%.