Graph augmentation and related problems: theory and practice
Graph augmentation and related problems: theory and practice
Post routing performance optimization via multi-link insertion and non-uniform wiresizing
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A fast and simple Steiner routing heuristic
Discrete Applied Mathematics - Special volume on VLSI
A uniform framework for approximating weighted connectivity problems
Proceedings of the tenth annual ACM-SIAM symposium on Discrete algorithms
Yield modeling and BEOL fundamentals
Proceedings of the 2001 international workshop on System-level interconnect prediction
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Research directions for coevolution of rules and routers
Proceedings of the 2003 international symposium on Physical design
Multilevel full-chip routing with testability and yield enhancement
Proceedings of the 2005 international workshop on System level interconnect prediction
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Steiner network construction for timing critical nets
Proceedings of the 43rd annual Design Automation Conference
TROY: track router with yield-driven wire planning
Proceedings of the 44th annual Design Automation Conference
Concurrent wire spreading, widening, and filling
Proceedings of the 44th annual Design Automation Conference
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Considering possible opens in non-tree topology wire delay calculation
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Utilizing redundancy for timing critical interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Redundant wire insertion for yield improvement
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Polaris: a system-level roadmapping toolchain for on-chip interconnection networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
How to consider shorts and guarantee yield rate improvement for redundant wire insertion
Proceedings of the 2009 International Conference on Computer-Aided Design
Resource-constrained timing-driven link insertion for critical delay reduction
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Resource-constrained link insertion for delay reduction
Integration, the VLSI Journal
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We propose to introduce redundant interconnects for manufacturing yield and reliability improvement. By introducing redundant interconnects, the potential for open faults is reduced at the cost of increased potential for short faults; overall, manufacturing yield and fault tolerance can be improved. We focus on a post-processing, tree augmentation approach which can be easily integrated in current physical design flows. Our contributions are as follows:• We formulate the problem as a variant of the classical 2-edge-connectivity augmentation problem in which we take into account such practical issues as wirelength increase budget, routing obstacles, and use of Steiner points.• We show that an optimum solution can always be found on the Hanan grid defined by the terminals and the corners of the feasible routing region.• We give a compact integer program formulation which, for up to 100 terminal nets, is solved in practical runtime by the commercial optimization package CPLEX.• We give a well-scaling greedy algorithm which has practical runtime up to 1,000 terminals, and comes on the average within 1--2% of the optimum computed by CPLEX.• We give a comprehensive experimental study comparing the solution quality and runtime of our methods with the best reported methods for 2-edge-connectivity augmentation, including a sophisticated heuristic based on minimum-weight branchings [9] and a recent genetic algorithm [14].Experiments on randomly generated and industry testcases show that our greedy augmentation method achieves significant increase in reliability (as measured by the percentage of biconnected tree edges) with very small increase in wirelength. For example, on 1,000 terminal nets the average percentage of biconnected tree edges is 34.19% for a wire-length increase of only 1%, and 87.73% for a wirelength increase of 20%. SPICE simulations on industry routed nets show that non-tree routing has the additional benefit of reducing maximum sink delay by an average of 28.26% compared to Steiner routing, and by an average of 3.72% compared to timing optimized routing. SPICE simulations further imply that non-tree routing has smaller delay variation due to process variability.