Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
Express Cubes: Improving the Performance of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Non-tree routing for reliability and yield improvement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
A Very Efficient Distributed Deadlock Detection Mechanism for Wormhole Networks
HPCA '98 Proceedings of the 4th International Symposium on High-Performance Computer Architecture
Leakage power modeling and optimization in interconnection networks
Proceedings of the 2003 international symposium on Low power electronics and design
A Delay Model and Speculative Architecture for Pipelined Routers
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Power-driven Design of Router Microarchitectures in On-chip Networks
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 2
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Variational delay metrics for interconnect timing analysis
Proceedings of the 41st annual Design Automation Conference
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Network on Chip Simulations for Benchmarking
IWSOC '04 Proceedings of the System-on-Chip for Real-Time Applications, 4th IEEE International Workshop
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Fault tolerance overhead in network-on-chip flow control schemes
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
VHDL-based simulation environment for Proteo NoC
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Design tradeoffs for tiled CMP on-chip networks
Proceedings of the 20th annual international conference on Supercomputing
Early wire characterization for predictable network-on-chip global interconnects
Proceedings of the 2007 international workshop on System level interconnect prediction
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
NoC Design and Implementation in 65nm Technology
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
NoC Topologies Exploration based on Mapping and Simulation Models
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Polaris: a system-level roadmapping toolchain for on-chip interconnection networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mesh routing topologies for multi-FPGA systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Network-on-Chip Architectures for Neural Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Third International Workshop on Network on Chip Architectures
A deadlock-free routing algorithm for dynamically reconfigurable Networks-on-Chip
Microprocessors & Microsystems
A NoC-based hybrid message-passing/shared-memory approach to CMP design
Microprocessors & Microsystems
Scalable network-on-chip architecture for configurable neural networks
Microprocessors & Microsystems
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Clustered NOC, a suitable design for group communications in Network on Chip
Computers and Electrical Engineering
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Networks-on-chip (NoCs) address the challenge to provide scalable communication bandwidth to tiled architectures in a power-efficient fashion. The 2-D mesh is currently the most popular regular topology used for on-chip networks in tile-based architectures, because it perfectly matches the 2-D silicon surface and is easy to implement. However, a number of limitations have been proved in the open literature, especially for long distance traffic. Two relevant variants of 2-D meshes are explored in this paper: high-dimensional and concentrated topologies. The novelty of our exploration framework includes the use of fast and accurate transaction level simulation to provide constraintsto the physical synthesis flow, which is integrated with standard industrial toolchains for accurate physical implementation. Interestingly, this work illustrates how effectively the compared topologies can handle synchronization-intensive traffic patterns and accounts for chip I/O interfaces.