Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
The case for a single-chip multiprocessor
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
IPPS '95 Proceedings of the 9th International Symposium on Parallel Processing
A Delay Model and Speculative Architecture for Pipelined Routers
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Power-driven Design of Router Microarchitectures in On-chip Networks
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Low-Latency Virtual-Channel Routers for On-Chip Networks
Proceedings of the 31st annual international symposium on Computer architecture
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
High-level power analysis for on-chip networks
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
A low latency router supporting adaptivity for on-chip interconnects
Proceedings of the 42nd annual Design Automation Conference
Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks
Proceedings of the 32nd annual international symposium on Computer Architecture
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Rotary router: an efficient architecture for CMP interconnection networks
Proceedings of the 34th annual international symposium on Computer architecture
Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
Software-directed combined cpu/link voltage scaling fornoc-based cmps
SIGMETRICS '08 Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Reducing the Interconnection Network Cost of Chip Multiprocessors
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Reducing Packet Dropping in a Bufferless NoC
Euro-Par '08 Proceedings of the 14th international Euro-Par conference on Parallel Processing
Tradeoffs in designing accelerator architectures for visual computing
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Rigel: an architecture and scalable programming interface for a 1000-core accelerator
Proceedings of the 36th annual international symposium on Computer architecture
Firefly: illuminating future network-on-chip with nanophotonics
Proceedings of the 36th annual international symposium on Computer architecture
Phastlane: a rapid transit optical routing network
Proceedings of the 36th annual international symposium on Computer architecture
Triplet-based topology for on-chip networks
WSEAS Transactions on Computers
Area-efficiency in CMP core design: co-optimization of microarchitecture and physical design
ACM SIGARCH Computer Architecture News
Analysis of photonic networks for a chip multiprocessor using scientific applications
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Silicon-photonic clos networks for global on-chip communication
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Exploring concentration and channel slicing in on-chip network router
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Region-based routing: a mechanism to support efficient routing algorithms in NoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scalable arbitration of partitioned bus interconnection networks in 3D-IC systems
Proceedings of the 2nd International Workshop on Network on Chip Architectures
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
EURASIP Journal on Embedded Systems
Low-cost router microarchitecture for on-chip networks
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
A cost-effective load-balancing policy for tile-based, massive multi-core packet processors
ACM Transactions on Embedded Computing Systems (TECS)
Flexible architectural support for fine-grain scheduling
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
An analysis of on-chip interconnection networks for large-scale chip multiprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
HiPC'07 Proceedings of the 14th international conference on High performance computing
Hybrid network on chip (HNoC): local buses with a global mesh architecture
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Evaluating Bufferless Flow Control for On-chip Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Design of High-Radix Clos Network-on-Chip
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Power-Efficient and High-Performance Multi-level Hybrid Nanophotonic Interconnect for Multicores
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A multilayer nanophotonic interconnection network for on-chip many-core communications
Proceedings of the 47th Design Automation Conference
Virtual channels vs. multiple physical networks: a comparative analysis
Proceedings of the 47th Design Automation Conference
Destination-based adaptive routing on 2D mesh networks
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Performance modeling of n-dimensional mesh networks
Performance Evaluation
A hybrid packet-circuit switched on-chip network based on SDM
Proceedings of the Conference on Design, Automation and Test in Europe
Group-caching for NoC based multicore cache coherent systems
Proceedings of the Conference on Design, Automation and Test in Europe
Power-performance analysis of networks-on-chip with arbitrary buffer allocation schemes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Weighted random oblivious routing on torus networks
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Design of a scalable nanophotonic interconnect for future multicores
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
On-Chip Network Evaluation Framework
Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis
Netrace: dependency-driven trace-based network-on-chip simulation
Proceedings of the Third International Workshop on Network on Chip Architectures
Proceedings of the Third International Workshop on Network on Chip Architectures
A power-efficient network on-chip topology
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Throughput-Effective On-Chip Networks for Manycore Accelerators
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
A NoC-based hybrid message-passing/shared-memory approach to CMP design
Microprocessors & Microsystems
A TDM slot allocation flow based on multipath routing in NoCs
Microprocessors & Microsystems
A workload-adaptive and reconfigurable bus architecture for multicore processors
International Journal of Reconfigurable Computing
Exascale computing technology challenges
VECPAR'10 Proceedings of the 9th international conference on High performance computing for computational science
Energy-optimized on-chip networks using reconfigurable shortcut paths
ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
A low-latency, high-throughput on-chip optical router architecture for future chip multiprocessors
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A composite and scalable cache coherence protocol for large scale CMPs
Proceedings of the international conference on Supercomputing
F2BFLY: an on-chip free-space optical network with wavelength-switching
Proceedings of the international conference on Supercomputing
HOPE: hotspot congestion control for Clos network on chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Prevention flow-control for low latency torus Networks-on-Chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
BLOCON: a bufferless photonic Clos Network-on-Chip architecture
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
A case for globally shared-medium on-chip interconnect
Proceedings of the 38th annual international symposium on Computer architecture
A case for heterogeneous on-chip interconnects for CMPs
Proceedings of the 38th annual international symposium on Computer architecture
Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees
Proceedings of the 38th annual international symposium on Computer architecture
Hardware/software co-design for energy-efficient seismic modeling
Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis
HPC-Mesh: A Homogeneous Parallel Concentrated Mesh for Fault-Tolerance and Energy Savings
Proceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems
3D NOC for many-core processors
Microelectronics Journal
On the use of multiplanes on a 2D mesh network-on-chip
ICA3PP'11 Proceedings of the 11th international conference on Algorithms and architectures for parallel processing - Volume Part II
A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Co-design of channel buffers and crossbar organizations in NoCs architectures
Proceedings of the International Conference on Computer-Aided Design
A high efficient on-chip interconnection network in SIMD CMPs
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Making-a-stop: A new bufferless routing algorithm for on-chip network
Journal of Parallel and Distributed Computing
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
FeatherWeight: low-cost optical arbitration with QoS support
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
A modular simulator framework for network-on-chip based manycore chips using UNISIM
Transactions on High-Performance Embedded Architectures and Compilers IV
Topology-Aware quality-of-service support in highly integrated chip multiprocessors
ISCA'10 Proceedings of the 2010 international conference on Computer Architecture
Proceedings of the 26th ACM international conference on Supercomputing
Enhancing effective throughput for transmission line-based bus
Proceedings of the 39th Annual International Symposium on Computer Architecture
Proceedings of the ACM SIGCOMM 2012 conference on Applications, technologies, architectures, and protocols for computer communication
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router
Microprocessors & Microsystems
Energy-guided exploration of on-chip network design for exa-scale computing
Proceedings of the International Workshop on System Level Interconnect Prediction
Handling global traffic in future CMP NoCs
Proceedings of the International Workshop on System Level Interconnect Prediction
APCR: an adaptive physical channel regulator for on-chip interconnects
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
ACM SIGCOMM Computer Communication Review - Special october issue SIGCOMM '12
Accurate on-chip router area modeling with kriging methodology
Proceedings of the International Conference on Computer-Aided Design
StreamTMC: Stream compilation for tiled multi-core architectures
Journal of Parallel and Distributed Computing
Efficient genetic based topological mapping using analytical models for on-chip networks
Journal of Computer and System Sciences
Physical-aware system-level design for tiled hierarchical chip multiprocessors
Proceedings of the 2013 ACM international symposium on International symposium on physical design
NOC-Out: Microarchitecting a Scale-Out Processor
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Research on half-mesh topology based on binary model and HTF-XY routing algorithm
International Journal of Computer Applications in Technology
A source-synchronous Htree-based network-on-chip
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Switch folding: network-on-chip routers with time-multiplexed output ports
Proceedings of the Conference on Design, Automation and Test in Europe
Wireless interconnect for board and chip level
Proceedings of the Conference on Design, Automation and Test in Europe
Exploring topologies for source-synchronous ring-based network-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Catnap: energy proportional multiple network-on-chip
Proceedings of the 40th Annual International Symposium on Computer Architecture
A heterogeneous multiple network-on-chip design: an application-aware approach
Proceedings of the 50th Annual Design Automation Conference
Semi-serial on-chip link implementation for energy efficiency and high throughput
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fast, source-synchronous ring-based network-on-chip design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Destination-based congestion awareness for adaptive routing in 2D mesh networks
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Journal of Electronic Testing: Theory and Applications
Designing on-chip networks for throughput accelerators
ACM Transactions on Architecture and Code Optimization (TACO)
Scalable high-radix router microarchitecture using a network switch organization
ACM Transactions on Architecture and Code Optimization (TACO)
Memory-centric system interconnect design with hybrid memory cubes
PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
Optimization of interconnects between accelerators and shared memories in dark silicon
Proceedings of the International Conference on Computer-Aided Design
Microprocessors & Microsystems
X-Network: An area-efficient and high-performance on-chip wormhole interconnect network
Microprocessors & Microsystems
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We develop detailed area and energy models for on-chip interconnection networks and describe tradeoffs in the design of efficient networks for tiled chip multiprocessors. Using these detailed models we investigate how aspects of the network architecture including topology, channel width, routing strategy, and buffer size affect performance and impact area and energy efficiency. We simulate the performance of a variety of on-chip networks designed for tiled chip multiprocessors implemented in an advanced VLSI process and compare area and energy efficiencies estimated from our models. We demonstrate that the introduction of a second parallel network can increase performance while improving efficiency, and evaluate different strategies for distributing traffic over the subnetworks. Drawing on insights from our analysis, we present a concentrated mesh topology with replicated subnetworks and express channels which provides a 24% improvement in area efficiency and a 48% improvement in energy efficiency over other networks evaluated in this study.