Silicon-photonic clos networks for global on-chip communication

  • Authors:

  • Ajay Joshi;Christopher Batten;Yong-Jin Kwon;Scott Beamer;Imran Shamim;Krste Asanovic;Vladimir Stojanovic

  • Affiliations:

  • Department of EECS, Massachusetts Institute of Technology, Cambridge, USA;Department of EECS, Massachusetts Institute of Technology, Cambridge, USA;Department of EECS, University of California, Berkeley, USA;Department of EECS, University of California, Berkeley, USA;Department of EECS, Massachusetts Institute of Technology, Cambridge, USA;Department of EECS, University of California, Berkeley, USA;Department of EECS, Massachusetts Institute of Technology, Cambridge, USA

  • Venue:
  • NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
  • Year:
  • 2009

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Abstract

Future manycore processors will require energy-efficient, high-throughput on-chip networks. Silicon-photonics is a promising new interconnect technology which offers lower power, higher bandwidth density, and shorter latencies than electrical interconnects. In this paper we explore using photonics to implement low-diameter non-blocking crossbar and Clos networks. We use analytical modeling to show that a 64-tile photonic Clos network consumes significantly less optical power, thermal tuning power, and area compared to global photonic crossbars over a range of photonic device parameters. Compared to various electrical on-chip networks, our simulation results indicate that a photonic Clos network can provide more uniform latency and throughput across a range of traffic patterns while consuming less power. These properties will help simplify parallel programming by allowing the programmer to ignore network topology during optimization.