The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
CMOS Photonics for High-Speed Interconnects
IEEE Micro
Design tradeoffs for tiled CMP on-chip networks
Proceedings of the 20th annual international conference on Supercomputing
A practical fast parallel routing architecture for Clos networks
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
On the Design of a Photonic Network-on-Chip
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Flattened Butterfly Topology for On-Chip Networks
IEEE Computer Architecture Letters
Corona: System Implications of Emerging Nanophotonic Technology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Silicon-photonic clos networks for global on-chip communication
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Power-Efficient and High-Performance Multi-level Hybrid Nanophotonic Interconnect for Multicores
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
METEOR: Hybrid photonic ring-mesh network-on-chip for multicore architectures
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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On-chip photonic waveguides have been proposed as a feasible replacement for the long interconnects that cause speed and power bottlenecks. Along with recent advancements in nanophotonic technologies, we believe that combining on-chip waveguides with high-radix Network on Chip (NoC) topologies is a promising way to improve NoC performance. In this paper, we propose the BLOCON (BufferLess phOtonic ClOs Network) to exploit silicon photonics. We propose a scheduling algorithm named Sustained and Informed Dual Round-Robin Matching (SIDRRM) to solve the output contention problem, and a path allocation scheme named Distributed and Informed Path Allocation (DIPA) to solve the Clos network routing problem. In the simulation results, we show that with SIDRRM and DIPA, BLOCON improves the delay and power performance of the compared electrical and photonic NoC architectures over synthetic traffic patterns and SPLASH-2 traces.