Flattened Butterfly Topology for On-Chip Networks

Authors:
John Kim;James Balfour;William J. Dally
Affiliations:
-;-;-
Venue:
IEEE Computer Architecture Letters
Year:
2007

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Abstract

With the trend towards increasing number of cores in a multicore processors, the on-chip network that connects the cores needs to scale efficiently. In this work, we propose the use of high-radix networks in on-chip networks and describe how the flattened butterfly topology can be mapped to on-chip networks. By using high-radix routers to reduce the diameter of the network, the flattened butterfly offers lower latency and energy consumption than conventional on-chip topologies. In addition, by properly using bypass channels in the flattened butterfly network, non-minimal routing can be employed without increasing latency or the energy consumption.