Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Express Cubes: Improving the Performance of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Self-Similar Network Traffic and Performance Evaluation
Self-Similar Network Traffic and Performance Evaluation
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Delay Model and Speculative Architecture for Pipelined Routers
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Current-mode signaling in deep submicrometer global interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
On-chip traffic modeling and synthesis for MPEG-2 video applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
Low-Latency Virtual-Channel Routers for On-Chip Networks
Proceedings of the 31st annual international symposium on Computer architecture
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Key research problems in NoC design: a holistic perspective
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A Virtual Channel Network-on-Chip for GT and BE traffic
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
The design and implementation of a low-latency on-chip network
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A Mesh-of-Trees Interconnection Network for Single-Chip Parallel Processing
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
Design tradeoffs for tiled CMP on-chip networks
Proceedings of the 20th annual international conference on Supercomputing
NoC Design and Implementation in 65nm Technology
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Flattened Butterfly Topology for On-Chip Networks
IEEE Computer Architecture Letters
Mesh-of-tree deterministic routing for network-on-chip architecture
Proceedings of the 18th ACM Great Lakes symposium on VLSI
3-D topologies for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Technology-Driven, Highly-Scalable Dragonfly Topology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation
IEEE Transactions on Computers
Polaris: a system-level roadmapping toolchain for on-chip interconnection networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scalability of network-on-chip communication architecture for 3-D meshes
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Network-on-chip architecture design based on mesh-of-tree deterministic routing topology
International Journal of High Performance Systems Architecture
An Application Mapping Technique for Butterfly-Fat-Tree Network-on-Chip
EAIT '11 Proceedings of the 2011 Second International Conference on Emerging Applications of Information Technology
Application-Specific Network-on-Chip synthesis with flexible router Placement
Journal of Systems Architecture: the EUROMICRO Journal
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Network-on-Chip (NoC) has emerged as a new paradigm to integrate large number of cores on a single silicon die. This paper presents a detailed study of Mesh-of-Tree (MoT) topology and explores its promise in communication infrastructure design for 2-D NoC. The performance and cost of MoT based NoC have been evaluated and compared with butterfly fat-tree (BFT) and two variants of mesh network for equal number of cores under same bisection width constraint. Simulation results under self-similar traffic show that MoT enjoys the advantage of having better performance than other topologies, whereas, it consumes lesser average packet energy than the mesh network that connects single core to each router. In the area front, MoT occupies almost similar area like mesh network connects single core to each router. The MoT network has also been evaluated under a set of real benchmark applications and compared with the above mentioned topologies. Simulation results under application specific traffic also show the competitive potential of MoT topology in NoC design. Moreover, due to lesser connectivity of the routers, synthesis result shows that MoT network can be operated at higher frequency than others. Taking all these facts into consideration, this paper establishes that like mesh and BFT, MoT can also be applied in designing NoC based systems. This paper also focuses on the limitations of MoT and other tree based topologies in NoC design in current technology and enumerates probable solutions to make them more acceptable.