Smart Memories: a modular reconfigurable architecture
Proceedings of the 27th annual international symposium on Computer architecture
Clock rate versus IPC: the end of the road for conventional microarchitectures
Proceedings of the 27th annual international symposium on Computer architecture
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A Delay Model and Speculative Architecture for Pipelined Routers
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Low-Latency Virtual-Channel Routers for On-Chip Networks
Proceedings of the 31st annual international symposium on Computer architecture
Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams
Proceedings of the 31st annual international symposium on Computer architecture
The Vector-Thread Architecture
Proceedings of the 31st annual international symposium on Computer architecture
Self-Timed Circuitry for Global Clocking
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
A Power and Energy Exploration of Network-on-Chip Architectures
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A Network of Time-Division Multiplexed Wiring for FPGAs
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Statistical Approach to NoC Design
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Reducing the Interconnection Network Cost of Chip Multiprocessors
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Reducing Packet Dropping in a Bufferless NoC
Euro-Par '08 Proceedings of the 14th international Euro-Par conference on Parallel Processing
Integration, the VLSI Journal
Dynamic packet fragmentation for increased virtual channel utilization in on-chip routers
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
An energy and performance exploration of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-cost router microarchitecture for on-chip networks
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
A method for calculating hard QoS guarantees for Networks-on-Chip
Proceedings of the 2009 International Conference on Computer-Aided Design
Hierarchical circuit-switched NoC for multicore video processing
Microprocessors & Microsystems
A practical low-latency router architecture with wing channel for on-chip network
Microprocessors & Microsystems
Comparative study of switching techniques for network-on-chip architecture
Proceedings of the 2011 International Conference on Communication, Computing & Security
Vertical interconnects squeezing in symmetric 3D mesh network-on-chip
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Static timing analysis for modeling QoS in networks-on-chip
Journal of Parallel and Distributed Computing
An improvement of router throughput for on-chip networks using on-the-fly virtual channel allocation
ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
NoC frequency scaling with flexible-pipeline routers
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Explicit modeling of control and data for improved NoC router estimation
Proceedings of the 49th Annual Design Automation Conference
A single-cycle output buffered router with layered switching for Networks-on-Chips
Computers and Electrical Engineering
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router
Microprocessors & Microsystems
APCR: an adaptive physical channel regulator for on-chip interconnects
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Designing best effort networks-on-chip to meet hard latency constraints
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
TornadoNoC: A lightweight and scalable on-chip network architecture for the many-core era
ACM Transactions on Architecture and Code Optimization (TACO)
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Many of the issues that will be faced by the designers of multi-billion transistor chips may be alleviated by the presence of a flexible global communication infrastructure. In the short term, such a network will provide scalable chip-wide communication and ease the complexity of handling multi-cycle communications. In the long term, the network will become a primary tool for optimising power and data transfers and for scheduling computations. This paper details the design and implementation of a low-latency on-chip network. The network's speculative routers are in the best case able to route flits in a single clock cycle, helping to minimise on-chip communication latencies and maximise the effectiveness of buffering resources. Results from our 180nm test chip demonstrate an inter-router data transfer rate in excess of 16Gbit/s for each link. In the best case each router hop adds just 1 clock cycle to the final communication latency.