Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Leakage power modeling and optimization in interconnection networks
Proceedings of the 2003 international symposium on Low power electronics and design
A Power and Performance Model for Network-on-Chip Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
The Future Evolution of High-Performance Microprocessors
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
The design and implementation of a low-latency on-chip network
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Low-power network-on-chip for high-performance SoC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Power and Energy Exploration of Network-on-Chip Architectures
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Implications of Rent's Rule for NoC Design and Its Fault-Tolerance
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Proximity coherence for chip multiprocessors
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Online allocation for contention-free-routing NoCs
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
A high efficient on-chip interconnection network in SIMD CMPs
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Predicting Coherence Communication by Tracking Synchronization Points at Run Time
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Dual-layer adaptive error control for network-on-chip links
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A TDM NoC supporting QoS, multicast, and fast connection set-up
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we explore the designs of a circuit -switched router, a wormhole router, a quality-of-service (QoS) supporting virtual channel router and a speculative virtual channel router and accurately evaluate the energy-performance tradeoffs they offer. Power results from the designs placed and routed in a 90-nm CMOS process show that all the architectures dissipate significant idle state power. The additional energy required to route a packet through the router is then shown to be dominated by the data path. This leads to the key result that, if this trend continues, the use of more elaborate control can be justified and will not be immediately limited by the energy budget. A performance analysis also shows that dynamic resource allocation leads to the lowest network latencies, while static allocation may be used to meet QoS goals. Combining the power and performance figures then allows an energy-latency product to be calculated to judge the efficiency of each of the networks. The speculative virtual channel router was shown to have a very similar efficiency to the wormhole router, while providing a better performance, supporting its use for general purpose designs. Finally, area metrics are also presented to allow a comparison of implementation costs.