Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Leakage power modeling and optimization in interconnection networks
Proceedings of the 2003 international symposium on Low power electronics and design
A Power and Performance Model for Network-on-Chip Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
The design and implementation of a low-latency on-chip network
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
The next resource war: computation vs. communication
Proceedings of the 2008 international workshop on System level interconnect prediction
Run-time power gating of on-chip routers using look-ahead routing
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Integration, the VLSI Journal
Flow-aware allocation for on-chip networks
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Dynamic packet fragmentation for increased virtual channel utilization in on-chip routers
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Power optimization for application-specific networks-on-chips: A topology-based approach
Microprocessors & Microsystems
An energy and performance exploration of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SCARAB: a single cycle adaptive routing and bufferless network
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Low power nanoscale buffer management for network on chip routers
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Network-on-Chip Architectures for Neural Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
Improved on-chip router analytical power and area modeling
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Scalable network-on-chip architecture for configurable neural networks
Microprocessors & Microsystems
Comparative study of switching techniques for network-on-chip architecture
Proceedings of the 2011 International Conference on Communication, Computing & Security
Reducing Network-on-Chip energy consumption through spatial locality speculation
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
The ReNoC Reconfigurable Network-on-Chip: Architecture, Configuration Algorithms, and Evaluation
ACM Transactions on Embedded Computing Systems (TECS)
Implications of electronics technology trends to algorithm design
VoCS'08 Proceedings of the 2008 international conference on Visions of Computer Science: BCS International Academic Conference
Explicit modeling of control and data for improved NoC router estimation
Proceedings of the 49th Annual Design Automation Conference
HANDS: heterogeneous architectures and networks-on-chip design and simulation
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
International Journal of Embedded and Real-Time Communication Systems
NBTI-aware design of NoC buffers
Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip
Sensor-wise methodology to face NBTI stress of NoC buffers
Proceedings of the Conference on Design, Automation and Test in Europe
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In this study, we analyse the move towards Networks-on- Chips from an energy perspective by accurately modelling a Circuit-Switched router, a Wormhole router and a speculative Virtual-Channel router in a 90nm CMOS process. All the routers are shown to dissipate significant idle state power. The additional energy required to route a packet through the router is then shown to be dominated by the data-path. This leads to the key result that, if this trend continues, the energy cost of more elaborate control will not be vast, making it easier to justify. Given effective clock-gating, this additional energy is also shown to be more or less independent of network congestion. Accurate speed and area metrics are also reported for the networks, which will allow a more complete comparison to be made across the NoC architectural space considered.