High-performance multi-queue buffers for VLSI communications switches
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The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
The SGI Origin: a ccNUMA highly scalable server
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Architecture and applications of the HEP mulitprocessor computer system
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Orion: a power-performance simulator for interconnection networks
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Low-Latency Virtual-Channel Routers for On-Chip Networks
Proceedings of the 31st annual international symposium on Computer architecture
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ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
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A Power and Energy Exploration of Network-on-Chip Architectures
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ICPADS '08 Proceedings of the 2008 14th IEEE International Conference on Parallel and Distributed Systems
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Hotnets-IX Proceedings of the 9th ACM SIGCOMM Workshop on Hot Topics in Networks
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Netrace: dependency-driven trace-based network-on-chip simulation
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MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Design of a performance enhanced and power reduced dual-crossbar Network-on-Chip (NoC) architecture
Microprocessors & Microsystems
Run-time energy management of manycore systems through reconfigurable interconnects
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FlexiBuffer: reducing leakage power in on-chip network routers
Proceedings of the 48th Design Automation Conference
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Proceedings of the International Conference on Computer-Aided Design
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Proceedings of the International Conference on Computer-Aided Design
Making-a-stop: A new bufferless routing algorithm for on-chip network
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ACM Transactions on Architecture and Code Optimization (TACO)
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LIGERO: A light but efficient router conceived for cache-coherent chip multiprocessors
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Low power flitwise routing in an unidirectional torus with minimal buffering
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Proceedings of the Conference on Design, Automation and Test in Europe
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Microprocessors & Microsystems
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As technology scaling drives the number of processor cores upward, current on-chip routers consume substantial portions of chip area and power budgets. Since existing research has greatly reduced router latency overheads and capitalized on available on-chip bandwidth, power constraints dominate interconnection network design. Recently research has proposed bufferless routers as a means to alleviate these constraints, but to date all designs exhibit poor operational frequency, throughput, or latency. In this paper, we propose an efficient bufferless router which lowers average packet latency by 17.6% and dynamic energy by 18.3% over existing bufferless on-chip network designs. In order to maintain the energy and area benefit of bufferless routers while delivering ultra-low latencies, our router utilizes an opportunistic processor-side buffering technique and an energy-efficient circuit-switched network for delivering negative acknowledgments for dropped packets.