Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams
Proceedings of the 31st annual international symposium on Computer architecture
A case for bufferless routing in on-chip networks
Proceedings of the 36th annual international symposium on Computer architecture
SCARAB: a single cycle adaptive routing and bufferless network
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Low-cost router microarchitecture for on-chip networks
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Low power flitwise routing in an unidirectional torus with minimal buffering
Proceedings of the Fifth International Workshop on Network on Chip Architectures
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Network on Chip(NoC) is an efficient communication fabric for multi-core systems. As on-chip core count increases, area and power consumed by NoCs have to be considered seriously. Enhancing performance of NoCs under strict area and power budgets is of practical concern. In this paper, we propose CAERUS, a low-cost router that incorporates a novel arbitration policy that balances the opportunities to inject flits and an optimized ejection policy. Experimental results show that CAERUS reduces traversal latency of the flits in the network and sustain the throughput at higher injection rates as compared to existing low-cost router designs. The area and power expenditures are comparable to existing low cost router architectures.