Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Route packets, not wires: on-chip inteconnection networks
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Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
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Power-driven Design of Router Microarchitectures in On-chip Networks
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An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
An Efficient Implementation of Distributed Routing Algorithms for NoCs
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
User-aware dynamic task allocation in networks-on-chip
Proceedings of the conference on Design, automation and test in Europe
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Proceedings of the 2008 ACM/IEEE conference on Supercomputing
Programming the Intel 80-core network-on-a-chip terascale processor
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Electro-Optical DSP of Tera Operations per Second and Beyond (Extended Abstract)
OSC '08 Proceedings of the 1st international workshop on Optical SuperComputing
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
ROAdNoC: runtime observability for an adaptive network on chip architecture
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Adaptive data compression for high-performance low-power on-chip networks
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Efficient unicast and multicast support for CMPs
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The modeling power of CINSim: Performance evaluation of interconnection networks
Computer Networks: The International Journal of Computer and Telecommunications Networking
A case for bufferless routing in on-chip networks
Proceedings of the 36th annual international symposium on Computer architecture
Triplet-based topology for on-chip networks
WSEAS Transactions on Computers
Networks-on-chip in emerging interconnect paradigms: Advantages and challenges
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Recursive partitioning multicast: A bandwidth-efficient routing for Networks-on-Chip
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
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The Future of Formal Methods and GALS Design
Electronic Notes in Theoretical Computer Science (ENTCS)
Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Router microarchitecture and scalability of ring topology in on-chip networks
Proceedings of the 2nd International Workshop on Network on Chip Architectures
SCARAB: a single cycle adaptive routing and bufferless network
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Low-cost router microarchitecture for on-chip networks
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
A case for dynamic frequency tuning in on-chip networks
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
A cost-effective load-balancing policy for tile-based, massive multi-core packet processors
ACM Transactions on Embedded Computing Systems (TECS)
Prototype design of cluster-based homogeneous multiprocessor system-on-chip
ASID'09 Proceedings of the 3rd international conference on Anti-Counterfeiting, security, and identification in communication
FinFET-based power simulator for interconnection networks
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Flexible DOR routing for virtualization of multicore chips
SOC'09 Proceedings of the 11th international conference on System-on-chip
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
XY-turn model for deadlock free routing in honeycomb networks-on-chip
APCC'09 Proceedings of the 15th Asia-Pacific conference on Communications
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Run-time task allocation considering user behavior in embedded multiprocessor networks-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Low-Latency and Memory-Efficient On-chip Network
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Power-Efficient and High-Performance Multi-level Hybrid Nanophotonic Interconnect for Multicores
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Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems
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Virtual point-to-point connections for NoCs
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A reconfigurable source-synchronous on-chip network for GALS many-core platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Improving FPGA performance for carry-save arithmetic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Trace-driven optimization of networks-on-chip configurations
Proceedings of the 47th Design Automation Conference
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Hotnets-IX Proceedings of the 9th ACM SIGCOMM Workshop on Hot Topics in Networks
A methodology for the characterization of process variation in NoC links
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient lookahead routing and header compression for multicasting in networks-on-chip
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Load balancing packets on a tile-based massive multi-core processor with S-NUCA
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Configurable links for runtime adaptive on-chip communication
Proceedings of the Conference on Design, Automation and Test in Europe
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
Group-caching for NoC based multicore cache coherent systems
Proceedings of the Conference on Design, Automation and Test in Europe
Adaptive and deadlock-free tree-based multicast routing for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of a scalable nanophotonic interconnect for future multicores
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Improved on-chip router analytical power and area modeling
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A generic adaptive path-based routing method for MPSoCs
Journal of Systems Architecture: the EUROMICRO Journal
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
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Hierarchical circuit-switched NoC for multicore video processing
Microprocessors & Microsystems
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Design of a performance enhanced and power reduced dual-crossbar Network-on-Chip (NoC) architecture
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A practical low-latency router architecture with wing channel for on-chip network
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RAFT: A router architecture with frequency tuning for on-chip networks
Journal of Parallel and Distributed Computing
Characterizing the impact of process variation on 45 nm NoC-based CMPs
Journal of Parallel and Distributed Computing
Iris: A hybrid nanophotonic network design for high-performance and low-power on-chip communication
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Prevention flow-control for low latency torus Networks-on-Chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Energy and reliability oriented mapping for regular Networks-on-Chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Link pipelining strategies for an application-specific asynchronous NoC
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Reducing Network-on-Chip energy consumption through spatial locality speculation
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
A case for globally shared-medium on-chip interconnect
Proceedings of the 38th annual international symposium on Computer architecture
A case for heterogeneous on-chip interconnects for CMPs
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DBAR: an efficient routing algorithm to support multiple concurrent applications in networks-on-chip
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3D integration for energy efficient system design
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Enabling system-level modeling of variation-induced faults in networks-on-chips
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Computers and Electrical Engineering
A low-latency modular switch for CMP systems
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A low-swing crossbar and link generator for low-power networks-on-chip
Proceedings of the International Conference on Computer-Aided Design
Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Fault tolerance analysis of mesh networks with uniform versus nonuniform node failure probability
Information Processing Letters
A modular simulator framework for network-on-chip based manycore chips using UNISIM
Transactions on High-Performance Embedded Architectures and Compilers IV
Benefits of selective packet discard in networks-on-chip
ACM Transactions on Architecture and Code Optimization (TACO)
Cost-effective power delivery to support per-core voltage domains for power-constrained processors
Proceedings of the 49th Annual Design Automation Conference
Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI
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A single-cycle output buffered router with layered switching for Networks-on-Chips
Computers and Electrical Engineering
HANDS: heterogeneous architectures and networks-on-chip design and simulation
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Enhancing effective throughput for transmission line-based bus
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Proceedings of the ACM SIGCOMM 2012 conference on Applications, technologies, architectures, and protocols for computer communication
Flexible router architecture for network-on-chip
Computers & Mathematics with Applications
PEPON: performance-aware hierarchical power budgeting for NoC based multicores
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
ACM SIGCOMM Computer Communication Review - Special october issue SIGCOMM '12
Efficient genetic based topological mapping using analytical models for on-chip networks
Journal of Computer and System Sciences
NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Addressing End-to-End Memory Access Latency in NoC-Based Multicores
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CARS: congestion-aware request scheduler for network interfaces in NoC-based manycore systems
Proceedings of the Conference on Design, Automation and Test in Europe
DeBAR: deflection based adaptive router with minimal buffering
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Semi-serial on-chip link implementation for energy efficiency and high throughput
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
UNISM: unified scheduling and mapping for general networks on chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal-constrained task allocation for interconnect energy reduction in 3-D homogeneous MPSoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CusNoC: fast full-chip custom NoC generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
AFRA: a low cost high performance reliable routing for 3D mesh NoCs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Ordering circuit establishment in multiplane NoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Deflection routing in 3D network-on-chip with limited vertical bandwidth
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The Journal of Supercomputing
Transport-layer-assisted routing for runtime thermal management of 3D NoC systems
ACM Transactions on Embedded Computing Systems (TECS)
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
Empirical and theoretical lower bounds on energy consumption for networks on chip
Proceedings of the Sixth International Workshop on Network on Chip Architectures
Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs
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CAERUS: an effective arbitration and ejection policy for routing in an unidirectional torus
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Design space exploration of thermal-aware many-core systems
Journal of Systems Architecture: the EUROMICRO Journal
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Microprocessors & Microsystems
X-Network: An area-efficient and high-performance on-chip wormhole interconnect network
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Unified reliability estimation and management of NoC based chip multiprocessors
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PAIS: Parallelism-aware interconnect scheduling in multicores
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The Journal of Supercomputing
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A multicore processor in 65-nm technology with 80 single-precision, floating-point cores delivers performance in excess of a teraflops while consuming less than 100 W. A 2D on-die mesh interconnection network operating at 5 GHz provides the high-performance communication fabric to connect the cores. The network delivers a bisection bandwidth of 2.56 Terabits per second and a per hop fall-through latency of 1 nanosecond.