FinFET-based power simulator for interconnection networks

Authors:
Chun-Yi Lee;Niraj K. Jha
Affiliations:
Princeton University, Princeton, NJ;Princeton University, Princeton, NJ
Venue:
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Year:
2008

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Abstract

Double-gate FETs, specifically FinFETs, are emerging as promising substitutes for bulk CMOS at the 32nm technology node and beyond because of the various obstacles to scaling faced by CMOS, such as short-channel effects, leakage power, and process variations. Another trend in chip multiprocessor design is incorporation of sophisticated on-chip interconnection networks. However, such networks are significant power-consumers. In this article, we address these two trends by presenting a power simulator for FinFET-based on-chip interconnection networks. It estimates both dynamic and leakage power. We present results for various FinFET design styles and temperatures (since leakage power changes drastically with temperature), and show that one FinFET design style may be much superior to another from the power consumption point of view.