A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Spider: A High-Speed Network Interconnect
IEEE Micro
Self-Tuned Congestion Control for Multiprocessor Networks
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Detailed design and evaluation of redundant multithreading alternatives
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
A comparative study of arbitration algorithms for the Alpha 21364 pipelined router
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
A Fault-Tolerant and Deadlock-Free Routing Protocol in 2D Meshes Based on Odd-Even Turn Model
IEEE Transactions on Computers
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
FIFO power optimization for on-chip networks
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism
Proceedings of the 31st annual international symposium on Computer architecture
Exploring Virtual Network Selection Algorithms in DSM Cache Coherence Protocols
IEEE Transactions on Parallel and Distributed Systems
Cost considerations in network on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
A Performance Evaluation of an Alpha EV7 Processing Node
International Journal of High Performance Computing Applications
Software-directed power-aware interconnection networks
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
A Recursion-Based Broadcast Paradigm in Wormhole Routed Networks
IEEE Transactions on Parallel and Distributed Systems
Energy savings through embedded processing on disk system
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Compiler-directed voltage scaling on communication links for reducing power consumption
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Journal of Parallel and Distributed Computing
Optimizing bus energy consumption of on-chip multiprocessors using frequent values
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Parallel, distributed and network-based processing
Fault-tolerant wormhole routing with 2 virtual channels in meshes
Journal of Computer Science and Technology
Throughput fairness in k-ary n-cube networks
ACSC '06 Proceedings of the 29th Australasian Computer Science Conference - Volume 48
Software-directed power-aware interconnection networks
ACM Transactions on Architecture and Code Optimization (TACO)
A buffered crossbar-based chip interconnection framework supporting quality of service
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Proceedings of the 4th international conference on Computing frontiers
Rotary router: an efficient architecture for CMP interconnection networks
Proceedings of the 34th annual international symposium on Computer architecture
Express virtual channels: towards the ideal interconnection fabric
Proceedings of the 34th annual international symposium on Computer architecture
Interconnect design considerations for large NUCA caches
Proceedings of the 34th annual international symposium on Computer architecture
Profile-driven energy reduction in network-on-chips
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks
IEEE Transactions on Parallel and Distributed Systems
Improving disk reuse for reducing power consumption
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
SAPP: scalable and adaptable peak power management in nocs
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Reducing the Interconnection Network Cost of Chip Multiprocessors
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Deadlock-Free Adaptive Routing in 2D Tori with a New Turn Model
ICA3PP '08 Proceedings of the 8th international conference on Algorithms and Architectures for Parallel Processing
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
FinFET-based power simulator for interconnection networks
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A routing methodology for dynamic fault tolerance in meshes and tori
HiPC'07 Proceedings of the 14th international conference on High performance computing
A scalable methodology for computing fault-free paths in InfiniBand torus networks
ISHPC'05/ALPS'06 Proceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems
An intra-chip free-space optical interconnect
Proceedings of the 37th annual international symposium on Computer architecture
Design of a High-Throughput Distributed Shared-Buffer NoC Router
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Microprocessors & Microsystems
A case for globally shared-medium on-chip interconnect
Proceedings of the 38th annual international symposium on Computer architecture
A design space exploration of transmission-line links for on-chip interconnect
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Online adaptive fault-tolerant routing in 2d torus
ISPA'05 Proceedings of the Third international conference on Parallel and Distributed Processing and Applications
Evaluation of interconnection network performance under heavy non-uniform loads
ICA3PP'05 Proceedings of the 6th international conference on Algorithms and Architectures for Parallel Processing
LIGERO: A light but efficient router conceived for cache-coherent chip multiprocessors
ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers
Edge chasing delayed consistency: pushing the limits of weak memory models
Proceedings of the 2012 ACM workshop on Relaxing synchronization for multicore and manycore scalability
Application-driven end-to-end traffic predictions for low power NoC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic directories: a mechanism for reducing on-chip interconnect power in multicores
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
The Alpha 21364 processor provides a high-performance, scalable, and reliable network architecture with a router that runs at 1.2 GHz and has a peak bandwidth of 22.4 Gbytes/s. Supporting configurations of up to 128 processors, this network architecture is well suited for communication-intensive server applications.