Data and computer communications (2nd ed.)
Data and computer communications (2nd ed.)
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Symmetric Crossbar Arbiters for VLSI Communication Switches
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Computers - Special issue on cache memory and related problems
On the Use of Virtual Channels in Networks of Workstations with Irregular Topology
IEEE Transactions on Parallel and Distributed Systems
Wormhole IP over (connectionless) ATM
IEEE/ACM Transactions on Networking (TON)
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
HIPIQS: A High-Performance Switch Architecture Using Input Queuing
IEEE Transactions on Parallel and Distributed Systems
Modeling of interconnection subsystems for massively parallel computers
Performance Evaluation
A comparative study of arbitration algorithms for the Alpha 21364 pipelined router
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
A Delay Model for Router Microarchitectures
IEEE Micro
The Alpha 21364 Network Architecture
IEEE Micro
Layered Shortest Path (LASH) Routing in Irregular System Area Networks
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
On the Design of a High-Performance Adaptive Router for CC-NUMA Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Hierarchical Simulation of a Multiprocessor Architecture
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Fast Dynamic Reconfiguration in Irregular Networks
ICPP '00 Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing
On the Design of Communication-Aware Task Scheduling Strategies for Heterogeneous Systems
ICPP '00 Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing
HIPIQS: A High-Performance Switch Architecture using Input Queuing
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
Latency, Occupancy, and Bandwidth in DSM Multiprocessors: A Performance Evaluation
IEEE Transactions on Computers
The Impact of Negative Acknowledgments in Shared Memory Scientific Applications
IEEE Transactions on Parallel and Distributed Systems
A Case Study in Networks-on-Chip Design for Embedded Video
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Multistage-Based Switching Fabrics for Scalable Routers
IEEE Transactions on Parallel and Distributed Systems
A first glance at Kilo-instruction based multiprocessors
Proceedings of the 1st conference on Computing frontiers
SMTp: An Architecture for Next-generation Scalable Multi-threading
Proceedings of the 31st annual international symposium on Computer architecture
Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism
Proceedings of the 31st annual international symposium on Computer architecture
Exploring Virtual Network Selection Algorithms in DSM Cache Coherence Protocols
IEEE Transactions on Parallel and Distributed Systems
Evaluation of queue designs for true fully adaptive routers
Journal of Parallel and Distributed Computing
A Memory-Effective Routing Strategy for Regular Interconnection Networks
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
Evaluating kilo-instruction multiprocessors
WMPI '04 Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture
A Performance Evaluation of an Alpha EV7 Processing Node
International Journal of High Performance Computing Applications
Routing Table Partitioning for Speedy Packet Lookups in Scalable Routers
IEEE Transactions on Parallel and Distributed Systems
Routing direction determination in regular networks based on configurable circuits
Future Generation Computer Systems
FIR: an efficient routing strategy for tori and meshes
Journal of Parallel and Distributed Computing - 19th International parallel and distributed processing symposium
Deadlock-free connection-based adaptive routing with dynamic virtual circuits
Journal of Parallel and Distributed Computing
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Communication Based Proactive Link Power Management
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Token tenure: PATCHing token counting using directory-based cache coherence
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
A case for bufferless routing in on-chip networks
Proceedings of the 36th annual international symposium on Computer architecture
Dynamic packet fragmentation for increased virtual channel utilization in on-chip routers
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Router designs for elastic buffer on-chip networks
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
Allocator implementations for network-on-chip routers
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
Routing direction determination in regular networks based on configurable circuits
Future Generation Computer Systems
An analysis of on-chip interconnection networks for large-scale chip multiprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Token tenure and PATCH: A predictive/adaptive token-counting hybrid
ACM Transactions on Architecture and Code Optimization (TACO)
Design of a performance enhanced and power reduced dual-crossbar Network-on-Chip (NoC) architecture
Microprocessors & Microsystems
DBAR: an efficient routing algorithm to support multiple concurrent applications in networks-on-chip
Proceedings of the 38th annual international symposium on Computer architecture
Packet chaining: efficient single-cycle allocation for on-chip networks
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Communication based proactive link power management
Transactions on High-Performance Embedded Architectures and Compilers IV
Globally Synchronized Frames for guaranteed quality-of-service in on-chip networks
Journal of Parallel and Distributed Computing
Switch folding: network-on-chip routers with time-multiplexed output ports
Proceedings of the Conference on Design, Automation and Test in Europe
PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
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The SGI SPIDER chip provides a high-speed, reliable switching network with a flexible interface and topology suitable for a variety of high-end applications. Six full-duplex ports and a nonblocking internal crossbar can sustain a data transfer rate of 4.8 Gbytes/sec, either between chips in a single chassis or between remote chassis over cables up to 5 meters long. Messages of arbitrary length travel over four independent virtual channels with 256 levels of priority, and are protected by CCITT-CRC with hardware retry. These features make the SGI SPIDER well suited to serve as an interprocessor communication fabric, a distributed graphics switch fabric, or a central switch for high-end networking applications.