Parallel programming in Split-C
Proceedings of the 1993 ACM/IEEE conference on Supercomputing
Hardware-software co-design and ESDA
DAC '94 Proceedings of the 31st annual Design Automation Conference
Incorporating cores into system-level specification
Proceedings of the 11th international symposium on System synthesis
Spider: A High-Speed Network Interconnect
IEEE Micro
A simulation environment for hardware-software codesign
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Hardware/Software Co-verification, an IP Vendors Viewpoint
ICCD '98 Proceedings of the International Conference on Computer Design
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When proposing new architectural enhancements, it is also important to account for the hardware complexity. To achieve this goal, we propose to model the new design in a hardware description language (HDL), synthesize the HDL code, and infer a realistic clock cycle which will be used in subsequent simulations. For accurate results, we develop a two-level hierarchical simulation technique, where an execution driven simulator (RSIM) and an HDL simulator (Verilog-XL) are coupled to evaluate an entire system. We detail the simulation process and show its impact on the design of an interconnect switch architecture for CC-NUMA multiprocessors.