Pipelined memory shared buffer for VLSI switches
SIGCOMM '95 Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Design and analysis of a novel fast packet switch: pipeline Banyan
IEEE/ACM Transactions on Networking (TON)
The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
Providing guaranteed services without per flow management
Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
IEEE Transactions on Computers
Tiny Tera: A Packet Switch Core
IEEE Micro
Spider: A High-Speed Network Interconnect
IEEE Micro
IEEE Micro
ATLAS: A Single-Chip ATM Switch for NOWs
CANPC '97 Proceedings of the First International Workshop on Communication and Architectural Support for Network-Based Parallel Computing
Scalable shared-buffering ATM switch with a versatile searchable queue
IEEE Journal on Selected Areas in Communications
A framework for optimizing the cost and performance of next-generation IP routers
IEEE Journal on Selected Areas in Communications
Matching output queueing with a combined input/output-queued switch
IEEE Journal on Selected Areas in Communications
Design issues for high-performance active routers
IEEE Journal on Selected Areas in Communications
Switch fabric design for high performance IP routers: a survey
Journal of Systems Architecture: the EUROMICRO Journal
Fault Tolerant Interleaved Switching Fabrics For Scalable High-Performance Routers
IEEE Transactions on Parallel and Distributed Systems
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Abstract--Rapidly growing demand for high-speed networks has prompted the investigation into scalable routers that are capable of forwarding data at the aggregate rate of multiterabits per second. Such a router contains many line cards (LCs) for admitting external links of various speeds. Those LCs are interconnected by a switching fabric to provide paths for packets to travel from arrival LCs to their respective departure LCs. The switching fabric employed in a router dictates the scalability and the overall performance of the router. It is thus crucial for future multiterabit routers to incorporate scalable switching fabrics capable of interconnecting large numbers of LCs. This work considers switching fabrics with distributed packet routing to achieve high scalability and low costs. Our fabrics are based on a multistage structure with different recirculation designs, where adjacent stages are interconnected according to the indirect n-cube connection style. They all compare favorably with an earlier multistage-based counterpart according to extensive simulation, in terms of performance measures of interest and hardware complexity. When queues are incorporated in the output ports of switching elements (SEs), the total number of stages required in our proposed fabrics to achieve a given performance level can be reduced substantially. The performance of those fabrics with output queues is evaluated under different "speedups驴 of the queues, where the speedup is the operating clock rate ratio of that at the SE core to that over external links. It is found via our simulation results that a small speedup of two is adequate for buffered switching fabrics comprising 4\times 8 SEs to deliver better performance than their nonbuffered counterparts with 50 percent more stages of SEs, when the fabric size is 256. The buffered switching fabrics under different traffic patterns are evaluated and discussed as well. Being scalable and of low costs, the proposed switching fabrics are ideally suitable for routers with large numbers of LCs.