Data structures and network algorithms
Data structures and network algorithms
High-performance multi-queue buffers for VLSI communications switches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
High-speed switch scheduling for local-area networks
ACM Transactions on Computer Systems (TOCS)
Scheduling algorithms for input-queued cell switches
Scheduling algorithms for input-queued cell switches
Scheduling multicast cells in an input-queued switch
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 1
Achieving 100% throughput in an input-queued switch
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 1
Multicast scheduling for input-queued switches
IEEE Journal on Selected Areas in Communications
A simulation study of IP switching
SIGCOMM '97 Proceedings of the ACM SIGCOMM '97 conference on Applications, technologies, architectures, and protocols for computer communication
IEEE/ACM Transactions on Networking (TON)
Fast and scalable layer four switching
Proceedings of the ACM SIGCOMM '98 conference on Applications, technologies, architectures, and protocols for computer communication
Fast address lookups using controlled prefix expansion
ACM Transactions on Computer Systems (TOCS)
Analysis of nonblocking ATM switches with multiple input queues
IEEE/ACM Transactions on Networking (TON)
The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
IP lookups using multiway and multicolumn search
IEEE/ACM Transactions on Networking (TON)
Field programmable port extender (FPX) for distributed routing and queuing
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
The UniMIN switch architecture for large-scale ATM switches
IEEE/ACM Transactions on Networking (TON)
Memory-efficient state lookups with fast updates
Proceedings of the conference on Applications, Technologies, Architectures, and Protocols for Computer Communication
LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs
Proceedings of the 38th annual Design Automation Conference
Flexible bandwidth allocation in high-capacity packet switches
IEEE/ACM Transactions on Networking (TON)
HIPIQS: A High-Performance Switch Architecture Using Input Queuing
IEEE Transactions on Parallel and Distributed Systems
Fair Scheduling in Internet Routers
IEEE Transactions on Computers
Packet-mode scheduling in input-queued cell-based switches
IEEE/ACM Transactions on Networking (TON)
Journal of High Speed Networks
Concurrent round-robin-based dispatching schemes for Clos-network switches
IEEE/ACM Transactions on Networking (TON)
Fair Scheduling for Input Buffered Switches
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
A Packet-Aware Non-interleaving Scheduling Algorithm with Multiple Classes for Input-Queued Switch
ICOIN '02 Revised Papers from the International Conference on Information Networking, Wireless Communications Technologies and Network Applications-Part I
Distributed Input and Deflection Routing Based Packet Switch Using Shuffle Pattern Network
NETWORKING '00 Proceedings of the IFIP-TC6 / European Commission International Conference on Broadband Communications, High Performance Networking, and Performance of Communication Networks
A near optimal scheduler for switch-memory-switch routers
Proceedings of the fifteenth annual ACM symposium on Parallel algorithms and architectures
A 320-Gb/s IP router with QoS control
ICCC '02 Proceedings of the 15th international conference on Computer communication
Distributed, Dynamic Control of Circuit-Switched Banyan Networks
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
HIPIQS: A High-Performance Switch Architecture using Input Queuing
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
Concurrent fault detection for a multiple-plane packet switch
IEEE/ACM Transactions on Networking (TON)
Multistage-Based Switching Fabrics for Scalable Routers
IEEE Transactions on Parallel and Distributed Systems
Multiway range trees: scalable IP lookup with fast updates
Computer Networks: The International Journal of Computer and Telecommunications Networking
Analysis of iSLIP scheduling algorithm for input-queuing switches
CompSysTech '04 Proceedings of the 5th international conference on Computer systems and technologies
Efficient Reduction of HOL Blocking in Multistage Networks
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 9 - Volume 10
FIFO-Based Multicast Scheduling Algorithm for Virtual Output Queued Packet Switches
IEEE Transactions on Computers
Pipelined two step iterative matching algorithms for CIOQ crossbar switches
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
A framework for the design, synthesis and cycle-accurate simulation of multiprocessor networks
Journal of Parallel and Distributed Computing - Special issue: Design and performance of networks for super-, cluster-, and grid-computing: Part I
Hardware Efficient Two Step Iterative Matching Algorithms for VOQ Switches
ICPADS '06 Proceedings of the 12th International Conference on Parallel and Distributed Systems - Volume 1
Towards an efficient switch architecture for high-radix switches
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
Algorithm-Hardware Codesign of Fast Parallel Round-Robin Arbiters
IEEE Transactions on Parallel and Distributed Systems
Rate and delay guarantees provided by Clos packet switches with load balancing
IEEE/ACM Transactions on Networking (TON)
High-radix crossbar switches enabled by proximity communication
Proceedings of the 2008 ACM/IEEE conference on Supercomputing
A two-stage hardware scheduler combining greedy and optimal scheduling
Journal of Parallel and Distributed Computing
Bandwidth guaranteed multicast scheduling for virtual output queued packet switches
Journal of Parallel and Distributed Computing
SPF: to improve the performance of packet-mode scheduling
Computer Communications
A QoS network architecture to interconnect large-scale VLSI neural networks
IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
Design of the switching controller for the high-capacity non-blocking internet router
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Characterizing user-level network virtualization: performance, overheads and limits
International Journal of Network Management
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Algorithms and theory of computation handbook
The Lotterybus on-chip communication architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
Preemptive packet-mode scheduling to improve TCP performance
IWQoS'05 Proceedings of the 13th international conference on Quality of Service
Efficient approach to merge and segment IP packets
ICCNMC'05 Proceedings of the Third international conference on Networking and Mobile Computing
Choice of inner switching mechanisms in terabit router
ICN'05 Proceedings of the 4th international conference on Networking - Volume Part I
Building a terabit router with XD networks
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Input queued switches for variable length packets: analysis for Poisson and self-similar traffic
Computer Communications
A high speed scheduler/controller for unbuffered banyan networks
Computer Communications
Fast parallel prefix logic circuits for n2n round-robin arbitration
Microelectronics Journal
An efficient single-iteration single-bit request scheduling algorithm for input-queued switches
Journal of Network and Computer Applications
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Tiny Tera is a small packet switch with an aggregate bandwidth of approximately 1 terabit per second. The CMOS-based, input-queued, fixed-size packet switch suits a wide range of applications such as a high-performance ATM switch, the core of an Internet router, or as a fast multiprocessor interconnect. Using off-the-shelf technology, we plan to demonstrate that a very high bandwidth switch can be built without the need for esoteric optical switching technology. By employing novel scheduling algorithms for both unicast and multicast traffic, the switch will have a maximum throughput close to 100%. Using novel high-speed, chip-to-chip serial link technology, we plan to reduce the physical size and complexity of the switch, as well as the system pin count.