Data structures and network algorithms
Data structures and network algorithms
An introduction to parallel algorithms
An introduction to parallel algorithms
High-speed switch scheduling for local-area networks
ACM Transactions on Computer Systems (TOCS)
The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
Broadband Packet Switching Technologies: A Practical Guide to ATM Switches and IP Routers
Broadband Packet Switching Technologies: A Practical Guide to ATM Switches and IP Routers
Round-robin arbiter design and generation
Proceedings of the 15th international symposium on System Synthesis
Tiny Tera: A Packet Switch Core
IEEE Micro
Saturn: a terabit packet switch using dual round robin
IEEE Communications Magazine
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Proceedings of the 47th Design Automation Conference
A low-latency modular switch for CMP systems
Microprocessors & Microsystems
Fast parallel prefix logic circuits for n2n round-robin arbitration
Microelectronics Journal
| Hi-index | 0.00 |
As a basic building block of a switch scheduler, a fast and fair arbiter is critical to the efficiency of the scheduler, which is the key to the performance of a high-speed switch or router. In this paper, we propose a parallel round-robin arbiter (PRRA) based on a simple binary search algorithm, which is specially designed for hardware implementation. We prove that our PRRA achieves round-robin fairness under all input patterns. We further propose an improved (IPRRA) design that reduces the timing of PRRA significantly. Simulation results with TSMC .18\mu m standard cell library show that PRRA and IPRRA can meet the timing requirement of a terabit 256\times256 switch. Both PRRA and IPRRA are much faster and simpler than the programmable priority encoder (PPE), a well-known round-robin arbiter design. We also introduce an additional design which combines PRRA and IPRRA and provides trade-offs in gate delay, wire delay, and circuit area. With the binary tree structure and high performance, our designs are scalable for large N and useful for implementing schedulers for high-speed switches and routers.