Scalable and fault-tolerant network-on-chip design usingthe quartered recursive diagonal torus topology

Authors:
Xianfang Tan;Lei Zhang;Shankar Neelkrishnan;Mei Yang;Yingtao Jiang;Yulu Yang
Affiliations:
University of Nevada, Las Vegas, Las Vegas, NV, USA;University of Nevada, Las Vegas, Las Vegas, NV, USA;University of Nevada, Las Vegas, Las Vegas, NV, USA;University of Nevada, Las Vegas, Las Vegas, NV, USA;University of Nevada, Las Vegas, Las Vegas, NV, USA;University of Nevada, Las Vegas, Las Vegas, China
Venue:
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Year:
2008

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Abstract

Network-on-a-chip (NoC) is an effective approach to connect and manage the communication between the variety of design elements and intellectual property blocks required in large and complex system-on-chips. In this paper, we propose a new NoC architecture, referred as the Quartered Recursive Diagonal Torus (QRDT), which is constructed by overlaying diagonal torus. Due to its small diameter and rich routing recourses, QRDT is determined to be well suitable to construct highly scalable NoCs. In QRDT, data packets can be routed through a proposed minimal routing algorithm based on the Johnson codes that have traditionally been used in finite state machine designs. It has been shown that this proposed routing algorithm with minor modifications is capable of handling the single link/node failure. The hardware cost of the proposed QRDT architecture and its associated routing algorithm is revealed by designing two QRDT routers which have been synthesized using TSMC 0.18¼m CMOS technology.