International Journal of High Performance Computing and Networking
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Architectures and routing schemes for optical network-on-chips
Computers and Electrical Engineering
Scheduling framework for real-time dependable NoC-based systems
SOC'09 Proceedings of the 11th international conference on System-on-chip
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The interconnection network plays an important role in the performance and energy consumption of a Network-on-Chip (NoC) system. In this paper, we propose a RDT(2,2,1)/驴-based interconnection network for NoC designs. RDT(2,2,1)/驴 is constructed by recursively overlaying 2-D diagonal meshes (torus). The number of layers needed for routing the links in RDT(2,2,1)/驴 is shown to be bounded at 6, which is feasible to be implemented with current and future VLSI technologies. With the innovative diagonal structure and its simple rank assignment, RDT(2,2,1)/驴 possesses the following features: recursive structure, smaller diameter and average distance, embedded mesh/torus topology, a constant node degree of 8, and robust routing schemes. These features make RDT(2,2,1)/驴 a promising solution for the interconnection network of NoC designs satisfying the requirements for scalability, energyefficiency, customizability, and fault-tolerance.