Proceedings of the conference on Design, automation and test in Europe - Volume 2
ParIS: a parameterizable interconnect switch for networks-on-chip
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Analysis and Implementation of Practical, Cost-Effective Networks on Chips
IEEE Design & Test
An event-based monitoring service for networks on chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Communication-driven task binding for multiprocessor with latency insensitive network-on-chip
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Application-specific network-on-chip architecture customization via long-range link insertion
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A design methodology for application-specific networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS)
The Power of Priority: NoC Based Distributed Cache Coherency
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A Study of NoC Exit Strategies
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Implementing DSP Algorithms with On-Chip Networks
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Routing table minimization for irregular mesh NoCs
Proceedings of the conference on Design, automation and test in Europe
A predictive NoC architecture for vision systems dedicated to image analysis
EURASIP Journal on Embedded Systems
Performance and resource optimization of NoC router architecture for master and slave IP cores
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A monitoring-aware network-on-chip design flow
Journal of Systems Architecture: the EUROMICRO Journal
3-D topologies for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Using adaptive routing to compensate for performance heterogeneity
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Reliable And Secure Chip Level Communication By Residue Number System Code
Journal of Integrated Design & Process Science
A system-level design methodology for application-specific networks-on-chip
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
On a web-graph-based micronetwork architecture for SoCs
International Journal of Computers and Applications
A modeling tool for simulating and design of on-chip network systems
Microprocessors & Microsystems
Reconfigurable Networks on Chip: DRNoC architecture
Journal of Systems Architecture: the EUROMICRO Journal
Priority based forced requeue to reduce worst-case latencies for bursty traffic
Proceedings of the Conference on Design, Automation and Test in Europe
Exploring programming model-driven QoS support for NoC-based platforms
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A methodology for design of unbuffered router microarchitecture for S-mesh NoC
NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
IEEE Transactions on Circuits and Systems Part I: Regular Papers
"It's a small world after all": noc performance optimization via long-range link insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GNLS: a hybrid on-chip communication architecture for SoC designs
International Journal of High Performance Systems Architecture
An ROBDD-based combinatorial method for the evaluation of yield of defect-tolerant systems-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Network-on-Chip routing algorithms by breaking cycles
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Concurrent hybrid switching for massively parallel systems-on-chip: the CYBER architecture
Proceedings of the 9th conference on Computing Frontiers
System-level application-specific NoC design for network and multimedia applications
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Static routing in symmetric real-time network-on-chips
Proceedings of the 20th International Conference on Real-Time and Network Systems
Costs and benefits of flexibility in spatial division circuit switched networks-on-chip
Proceedings of the Sixth International Workshop on Network on Chip Architectures
Early-phase performance exploration of embedded systems with ABSOLUT framework
Journal of Systems Architecture: the EUROMICRO Journal
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We propose a communication protocol stack to be used inNostrum, our Network on Chip (NoC) architecture. In orderto aid the designer in the selection process of what parts ofprotocols, and their respective facilities, to include, a layeredapproach to communication is taken. A nomenclaturefor describing the individual layers' interfaces and servicedefinitions of the layers in the protocol stack is suggestedand used. The concept includes support for best effort trafficpacket delivery as well as support for guaranteed bandwidthtraffic, using virtual circuits. Furthermore anapplication to NoC adapter is defined, as part of theResource to Network Interface, and is used to communicatebetween the Nostrumprotocol stack and the application.An industrial example has been implemented, simulated,and the results justifies the suggested layered approach.