Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
SILENT: serialized low energy transmission coding for on-chip interconnection networks
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the 43rd annual Design Automation Conference
Increasing the throughput of an adaptive router in network-on-chip (NoC)
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
A buffered crossbar-based chip interconnection framework supporting quality of service
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Using the inter- and intra-switch regularity in NoC switch testing
Proceedings of the conference on Design, automation and test in Europe
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2007 workshop on Multimodal interfaces in semantic interaction
A practical design and implementation of on-chip NI for integrating bus based IP legacies
IMCAS'07 Proceedings of the 6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems
ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Design of a router for network-on-chip
International Journal of High Performance Systems Architecture
The ReNoC Reconfigurable Network-on-Chip: Architecture, Configuration Algorithms, and Evaluation
ACM Transactions on Embedded Computing Systems (TECS)
Asynchronous switching for low-power networks-on-chip
Microelectronics Journal
Hi-index | 0.00 |
This article describes design issues in three chips that exploit star and meshnetworks, with the objective of comparing area and energy costs. The authorspresent new solutions based on mesochronous communication and burstpacket transactions.