Segmented bus design for low-power systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A survey of techniques for energy efficient on-chip communication
Proceedings of the 40th annual Design Automation Conference
Leakage power modeling and optimization in interconnection networks
Proceedings of the 2003 international symposium on Low power electronics and design
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
A low-power crossroad switch architecture and its core placement for network-on-chip
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Design, Synthesis, and Test of Networks on Chips
IEEE Design & Test
Analysis and Implementation of Practical, Cost-Effective Networks on Chips
IEEE Design & Test
Area - Time - Power and Design effort: the basic tradeoffs in Application Specific Systems
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
Architectural energy optimization by bus splitting
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Implementation of a self-timed segmented bus
IEEE Design & Test
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Trend and Challenge on System-on-a-Chip Designs
Journal of Signal Processing Systems
Design Trade-offs in Customized On-chip Crossbar Schedulers
Journal of Signal Processing Systems
Reliable network-on-chip design for multi-core system-on-chip
The Journal of Supercomputing
Area and power-efficient innovative congestion-aware Network-on-Chip architecture
Journal of Systems Architecture: the EUROMICRO Journal
A single-cycle output buffered router with layered switching for Networks-on-Chips
Computers and Electrical Engineering
Costs and benefits of flexibility in spatial division circuit switched networks-on-chip
Proceedings of the Sixth International Workshop on Network on Chip Architectures
Supporting faulty banks in NUCA by NoC assisted remapping mechanisms
The Journal of Supercomputing
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NOC architectures have to deliver good latency-throughput performance in the face of very tight power and area budgets. However, the latency and the power consumption for transferring information down the transmitter stack, through the channel, and up the receiver stack might be unacceptably high. In this paper, we evaluate the designs of packet-switched and the proposed circuit-switched NOCs in detail, and we advocate using circuit-switched NOC as it is more attractive for application-specific SOC designs because of communication localization. We implement and synthesize the designs of packet-switched and circuit-switched NOCs, and we take multimedia applications as our case studies. The experimental results show that the area, latency and the energy consumption of packet-switched NOC are much larger than that of circuit-switched NOC.