Segmented bus design for low-power systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Chip-set for video display of multimedia information
IEEE Transactions on Consumer Electronics
Implementation of a self-timed segmented bus
IEEE Design & Test
Proceedings of the 43rd annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Software-directed combined cpu/link voltage scaling fornoc-based cmps
SIGMETRICS '08 Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
A hybrid packet-circuit switched on-chip network based on SDM
Proceedings of the Conference on Design, Automation and Test in Europe
Reliable network-on-chip design for multi-core system-on-chip
The Journal of Supercomputing
Explicit modeling of control and data for improved NoC router estimation
Proceedings of the 49th Annual Design Automation Conference
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As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the SoCs will be heterogeneous in nature with widely varying functionality and communication requirements. The communication topology should possibly match communication workflows among these components. In this paper, we first propose an interconnection architecture for SoC, which uses crossroad switches to construct a dedicated communication path dynamically between any two cores. We then present a design methodology for constructing network on chip (NoC) for application-specific computer systems with profiled communication characteristics. We design a core placement tool, which automatically maps cores to a communication topology such that we can minimize the total communication energy. Experimental results show that the design methodology can generate optimized on-chip networks with fewer resources than meshes and tori, and the power saving approximates to 40%