Scheduling precedence graphs in systems with interprocessor communication times
SIAM Journal on Computing
Implementing discrete mathematics: combinatorics and graph theory with Mathematica
Implementing discrete mathematics: combinatorics and graph theory with Mathematica
Multiprocessor scheduling to account for interprocessor communication
Multiprocessor scheduling to account for interprocessor communication
Task scheduling in parallel and distributed systems
Task scheduling in parallel and distributed systems
IEEE Transactions on Parallel and Distributed Systems
Optimal Scheduling Algorithm for Distributed-Memory Machines
IEEE Transactions on Parallel and Distributed Systems
On Exploiting Task Duplication in Parallel Program Scheduling
IEEE Transactions on Parallel and Distributed Systems
Interconnect pipelining in a throughput-intensive FPGA architecture
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Impact of Workload and System Parameters on Next Generation Cluster Scheduling Mechanisms
IEEE Transactions on Parallel and Distributed Systems
Topological Properties of OTIS-Networks
IEEE Transactions on Parallel and Distributed Systems
Code Generation for Embedded Processors
Code Generation for Embedded Processors
Embedded Multiprocessors: Scheduling and Synchronization
Embedded Multiprocessors: Scheduling and Synchronization
Computers and Intractability; A Guide to the Theory of NP-Completeness
Computers and Intractability; A Guide to the Theory of NP-Completeness
Link contention-constrained scheduling and mapping of tasks
Cluster Computing
PipeRoute: a pipelining-aware router for FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
IEEE Transactions on Parallel and Distributed Systems
RaPiD - Reconfigurable Pipelined Datapath
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Mesh routing topologies for multi-FPGA systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A low-power crossroad switch architecture and its core placement for network-on-chip
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
System-Level Design Methodology with Direct Execution For Multiprocessors on SoPC
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Proceedings of the 43rd annual Design Automation Conference
NoC Design and Implementation in 65nm Technology
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
MOCDEX: multiprocessor on chip multiobjective design space exploration with direct execution
EURASIP Journal on Embedded Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Computers and Electrical Engineering
Optimizing scheduling and intercluster connection for application-specific DSP processors
IEEE Transactions on Signal Processing
Reliable network-on-chip design for multi-core system-on-chip
The Journal of Supercomputing
| Hi-index | 0.01 |
As transistor sizes shrink, interconnects represent an increasing bottleneck for chip designers. Several groups are developing new interconnection methods and system architectures to cope with this trend. New architectures require new methods for high-level application mapping and hardware/software codesign. In this paper, we present high-level scheduling and interconnect topology synthesis techniques for embedded multiprocessor systems-on-chip that are streamlined for one or more digital signal processing applications. That is, we seek to synthesize an application-specific interconnect topology. We show that flexible interconnect topologies utilizing low-hop communication between processors offer advantages for reduced power and latency. We show that existing multiprocessor scheduling algorithms can deadlock if the topology graph is not strongly connected, or if a constraint is imposed on the maximum number of hops allowed for communication. We detail an efficient algorithm that can be used in conjunction with existing scheduling algorithms for avoiding this deadlock. We show that it is advantageous to perform application scheduling and interconnect synthesis jointly, and present a probabilistic scheduling/interconnect algorithm that utilizes graph isomorphism to pare the design space.