Proceedings of the 38th annual Design Automation Conference
Introducing Core-Based System Design
IEEE Design & Test
Automating the Design of SOCs Using Cores
IEEE Design & Test
A multiobjective optimization model for exploring multiprocessor mappings of process networks
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Multiobjective Design of Embedded Processors on FPGA Platforms
ICDCSW '04 Proceedings of the 24th International Conference on Distributed Computing Systems Workshops - W7: EC (ICDCSW'04) - Volume 7
The future of multiprocessor systems-on-chips
Proceedings of the 41st annual Design Automation Conference
Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
An automated exploration framework for FPGA-based soft multiprocessor systems
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Evolutionary Algorithms for Solving Multi-Objective Problems (Genetic and Evolutionary Computation)
Evolutionary Algorithms for Solving Multi-Objective Problems (Genetic and Evolutionary Computation)
Multiobjective evolutionary algorithms: a comparative case studyand the strength Pareto approach
IEEE Transactions on Evolutionary Computation
A fast and elitist multiobjective genetic algorithm: NSGA-II
IEEE Transactions on Evolutionary Computation
Evaluating large system-on-chip on multi-FPGA platform
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
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Contrary to ASIC design where resources can be tuned with respect to the need of the designer, systems on programmable chip SoPC (FPGA) have to make best use of 'off the shelf devices', where main resources are fixed. In this regard, embedded memories are of tremendous value because of their low latency. These embedded memories are not only used for data and program storage but also for all sorts of memory usage e.g. FIFO used by IP interfaces for bus and network on chip connection. The problem addressed by this paper is the optimal sizing of queues in the framework of SoPC. Current SoC design tools are of little help to define the most adequate size for these FIFOs and the large design space coupled with excessive simulation times make it even more difficult. We propose in this paper an automatic tuning technique of queue sizes in IP interfaces for system on programmable chip with hardware in the loop execution. An application of our technique on Virtex-II SoPC is described.