Evaluating large system-on-chip on multi-FPGA platform

Authors:
Ari Kulmala;Erno Salminen;Timo D. Hämäläinen
Affiliations:
Tampere University of Technology, Institute of Digital and Computer Systems, Tampere, Finland;Tampere University of Technology, Institute of Digital and Computer Systems, Tampere, Finland;Tampere University of Technology, Institute of Digital and Computer Systems, Tampere, Finland
Venue:
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Year:
2007

Citing 7
Cited 3

Implementation of BEE: a real-time large-scale hardware emulation engine

FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Mapping Multi-Million Gate SoCs on FPGAs: Industrial Methodology and Experience

Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Scalable Parallel SoC Architecture for Network Processors

ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
System-Level Design Methodology with Direct Execution For Multiprocessors on SoPC

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
HIBI Communication Network for System-on-Chip

Journal of VLSI Signal Processing Systems
A Scalable FPGA-based Multiprocessor

FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Scalable MPEG-4 encoder on FPGA multiprocessor SOC

EURASIP Journal on Embedded Systems

Evaluating SoC Network Performance in MPEG-4 Encoder

Journal of Signal Processing Systems
A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA

SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Reconfigurable multiprocessor systems: a review

International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a configurable base architecture tailorable for different applications. It allows simple and rapid way to evaluate and prototype large Multi-Processor System-on-Chip architectures on multiple FPGAs with support to Globally Asynchronous Locally Synchronous scheme. It allows early hardware/software co-verification and optimization. The architecture abstracts the underlying hardware details from the processors so that knowledge about the exact locations of individual components are not required for communication. Implemented example architecture contains 58 IP blocks, including 35 Nios II soft processors. As a proof of concept, a MPEG-4 video encoder is run on the example architecture.