GCA: Global Cellular Automata. A Flexible Parallel Model
PaCT '01 Proceedings of the 6th International Conference on Parallel Computing Technologies
GCA: A Massively Parallel Model
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
A Comparison of Five Different Multiprocessor SoC Bus Architectures
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
FPGA Implementations of the Massively Parallel GCA Model
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 14 - Volume 15
Theory of Self-Reproducing Automata
Theory of Self-Reproducing Automata
Evaluating large system-on-chip on multi-FPGA platform
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
A multiprocessor architecture for the massively parallel model GCA
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
The massively parallel computing model GCA
Euro-Par 2010 Proceedings of the 2010 conference on Parallel processing
An FPGA-based heterogeneous coarse-grained dynamically reconfigurable architecture
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
| Hi-index | 0.00 |
The GCA (Global Cellular Automata) model consists of a collection of cells which change their states synchronously depending on the states of their neighbors like in the classical CA (Cellular Automata) model. In differentiation to the CA model the neighbors are not fixed and local, they are variable and global. The GCA model is applicable to a wide range of parallel algorithms. In this paper a general purpose multiprocessor architecture for the massively parallel GCA model is presented. In contrast to a special purpose implementation of a GCA algorithm the multiprocessor system allows the implementation in a flexible way through programming. The architecture mainly consists of a set of processors (Nios II) and a network. The Nios II features a general-purpose RISC CPU architecture designed to address a wide range of applications. The network is a well-known omega network. Only read-accesses through the network are necessary in the GCA model leading to a simplified structure. A system with up to 32 processors was implemented as a prototype on an FPGA. The analysis and implementation results have shown that the performance of the system scales with the number of processors.