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PathFinder: a negotiation-based performance-driven router for FPGAs
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ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
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A decade of reconfigurable computing: a visionary retrospective
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VPR: A new packing, placement and routing tool for FPGA research
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UMC '02 Proceedings of the Third International Conference on Unconventional Models of Computation
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DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures
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SPR: an architecture-adaptive CGRA mapping tool
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A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing
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Parallel Routing Algorithm for Extra Level Omega Networks on Reconfigurable Systems
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A graph drawing based spatial mapping algorithm for coarse-grained reconfigurable architectures
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Coarse-grained reconfigurable architecture has emerged as a promising model for embedded systems as a solution to reduce the complexity of FPGA synthesis and mapping steps, consequently reducing reconfiguration time. Despite these advantages, CGRA usage has been limited due to the lack of commercial CGRA circuits. This work proposes a virtual and dynamic CGRA implemented on top of an FPGA. This approach allows the usage of commercial-off-the-shelf FPGA devices combined with the advantages of CGRAs. The proposed architecture consists of a set of heterogeneous functional units (FU) and a global interconnection network. The global network allows any FU to be used at each cycle, which reduces significantly the placement complexity. In addition, we introduce a polynomial mapping algorithm which includes scheduling, placement and routing steps (SPR). Moreover, the proposed approach performs a very fast placement and routing in comparison to similar CGRA approaches. The three SPR steps are computed in few milliseconds. The feasibility of this approach is demonstrated for a suite of digital signal processing benchmarks.