WaveScalar

  • Authors:
  • Steven Swanson;Ken Michelson;Andrew Schwerin;Mark Oskin

  • Affiliations:
  • Computer Science and Engineering, University of Washington;Computer Science and Engineering, University of Washington;Computer Science and Engineering, University of Washington;Computer Science and Engineering, University of Washington

  • Venue:
  • Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
  • Year:
  • 2003

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Abstract

Silicon technology will continue to provide an exponential increasein the availability of raw transistors. Effectively translatingthis resource into application performance, however,is an open challenge. Ever increasing wire-delay relativeto switching speed and the exponential cost of circuit complexitymake simply scaling up existing processor designs futile.In this paper, we present an alternative to superscalardesign, WaveScalar. WaveScalar is a dataflow instructionset architecture and execution model designed for scalable,low-complexity/high-performance processors. WaveScalar isunique among dataflow architectures in efficiently providingtraditional memory semantics. At last, a dataflow machinecan run "real-world" programs, written in any language,without sacrificing parallelism.The WaveScalar ISA is designed to run on an intelligentmemory system. Each instruction in a WaveScalar binary executesin place in the memory system and explicitly communicateswith its dependents in dataflow fashion. WaveScalararchitectures cache instructions and the values they operateon in a WaveCache, a simple grid of "alu-in-cache" nodes.By co-locating computation and data in physical space, theWaveCache minimizes long wire, high-latency communication.This paper introduces the WaveScalar instruction setand evaluates a simulated implementation based on currenttechnology. Results for the SPEC and Mediabench applicationsdemonstrate that the WaveCache out-performs an aggressivelyconfigured superscalar design by 2-7 times, withample opportunities for future optimizations.