Proceedings of the International Sympoisum on Theoretical Programming
First version of a data flow procedure language
Programming Symposium, Proceedings Colloque sur la Programmation
A data flow language for operating systems programming
Proceeding of ACM SIGPLAN - SIGOPS interface meeting on Programming languages - operating systems
A GRAPH MODEL FOR PARALLEL COMPUTATIONS
A GRAPH MODEL FOR PARALLEL COMPUTATIONS
The Manchester prototype dataflow computer
Communications of the ACM - Special section on computer architecture
A Formal Definition of Data Flow Graph Models
IEEE Transactions on Computers
Implementation and evaluation of a list-processing-oriented data flow machine
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
HPSm, a high performance restricted data flow architecture having minimal functionality
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
HPS, a new microarchitecture: rationale and introduction
MICRO 18 Proceedings of the 18th annual workshop on Microprogramming
ACM SIGARCH Computer Architecture News
ACM Computing Surveys (CSUR)
Analytical modeling and architectural modifications of a dataflow computer
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
On tuning the microarchitecture of an HPS implementation of the VAX
ACM SIGMICRO Newsletter
Tokenless static data flow using associative templates
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
Conception, evolution, and application of functional programming languages
ACM Computing Surveys (CSUR)
The Epsilon dataflow processor
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Performance Evaluation of a Dataflow Architecture
IEEE Transactions on Computers
A hands-on dataflow architecture/programming course
ACM SIGCSE Bulletin
Task-Flow Architecture for WSI Parallel Processing
Computer - Special issue on wafer-scale integration
On tuning the microarchitecture of an HPS implementation of the VAX
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
The object flow model for data-based simulation
WSC '93 Proceedings of the 25th conference on Winter simulation
Monsoon: an explicit token-store architecture
25 years of the international symposia on Computer architecture (selected papers)
Processor allocation strategies for multiprocessor database machines
ACM Transactions on Database Systems (TODS)
SHAPE: a highly adaptable and parallel system
CSC '86 Proceedings of the 1986 ACM fourteenth annual conference on Computer science
Data-Driven and Demand-Driven Computer Architecture
ACM Computing Surveys (CSUR)
On Parsing and Compiling Arithmetic Expressions on Vector Computers
ACM Transactions on Programming Languages and Systems (TOPLAS)
ACM Transactions on Programming Languages and Systems (TOPLAS)
Deleting Irrelevant Tasks in an Expression-Oriented Multiprocessor System
ACM Transactions on Programming Languages and Systems (TOPLAS)
Asynchrony in parallel computing: from dataflow to multithreading
Progress in computer research
Para-functional programming: a paradigm for programming multiprocessor systems
POPL '86 Proceedings of the 13th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
A design space evaluation of grid processor architectures
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Asynchrony in parallel computing: from dataflow to multithreading
Progress in computer research
Unbounded speed variability in distributed communication systems
POPL '82 Proceedings of the 9th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Design considerations for data-flow database machines
SIGMOD '80 Proceedings of the 1980 ACM SIGMOD international conference on Management of data
Analysis of integration models for service composition
WOSP '02 Proceedings of the 3rd international workshop on Software and performance
A History of Data-Flow Languages
IEEE Annals of the History of Computing
Some thoughts on data flow architectures
ACM SIGARCH Computer Architecture News
On the working set concept for data-flow machines
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A data driven system based on a microprogrammed processor module
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Switching strategies in a class of packet switching networks
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A system architecture for the concurrent evaluation of applicative program expressions
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Asynchronous and clocked control structures for VLSI based interconnection networks
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
MP/C: A multiprocessor/computer architecture
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Optimal processor interconnection topologies
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
MANIP-a parallel computer system for implementing branch and bound algorithms
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
An architecture for extended abstract data flow
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
A multi-processor reduction machine for user-defined reduction languages.
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
The MuNet: A scalable decentralized architecture for parallel computation
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
The Apiary network architecture for knowledgeable systems
LFP '80 Proceedings of the 1980 ACM conference on LISP and functional programming
Compilation techniques for a control-flow concurrent LISP system
LFP '80 Proceedings of the 1980 ACM conference on LISP and functional programming
A concurrent computer architecture and a ring based implementation
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
A language implementation design for a multiprocessor computer system
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
A hierarchical, restructurable multi-microprocessor architecture
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
A computer simulation facility for packet communication architecture
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
Parallel processing and data driven implementation of a relational data base system
ACM '76 Proceedings of the 1976 annual conference
Indeterminacy, monitors, and dataflow
SOSP '77 Proceedings of the sixth ACM symposium on Operating systems principles
Real time resource allocation in distributed systems
PODC '82 Proceedings of the first ACM SIGACT-SIGOPS symposium on Principles of distributed computing
Methods for system simulation on a restricted data flow architecture
ACM '81 Proceedings of the ACM '81 conference
Instruction reference patterns in data flow programs
ACM '80 Proceedings of the ACM 1980 annual conference
Methodology for designing a computer architecture
ACM SIGARCH Computer Architecture News
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Advances in dataflow programming languages
ACM Computing Surveys (CSUR)
CODACS Prototype: A Platform-Processor for CHIARA Programs
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 13 - Volume 14
A preliminary survey of artificial intelligence machines
ACM SIGART Bulletin
Encyclopedia of Computer Science
An Efficient Way of Passing of Data in a Multithreaded Scheduled Dataflow Architecture
HPCASIA '05 Proceedings of the Eighth International Conference on High-Performance Computing in Asia-Pacific Region
Compiling for EDGE Architectures
Proceedings of the International Symposium on Code Generation and Optimization
Area-Performance Trade-offs in Tiled Dataflow Architectures
Proceedings of the 33rd annual international symposium on Computer Architecture
Modeling instruction placement on a spatial architecture
Proceedings of the eighteenth annual ACM symposium on Parallelism in algorithms and architectures
Reducing control overhead in dataflow architectures
Proceedings of the 15th international conference on Parallel architectures and compilation techniques
A spatial path scheduling algorithm for EDGE architectures
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Instruction scheduling for a tiled dataflow architecture
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
JDA: a step towards large-scale reuse on the web
Companion to the 21st ACM SIGPLAN symposium on Object-oriented programming systems, languages, and applications
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
ACM Transactions on Computer Systems (TOCS)
Asynchronous and Clocked Control Structures for VSLI Based Interconnection Networks
IEEE Transactions on Computers
The Piecewise Data Flow Architecture: Architectural Concepts
IEEE Transactions on Computers
MP/C: A Multiprocessor/Computer Architecture
IEEE Transactions on Computers
A Flow Analysis Procedure for the Translation of High-Level Languages to a Data Flow Language
IEEE Transactions on Computers
A Data Flow Computer Architecture with Program and Token Memories
IEEE Transactions on Computers
Performance of a Simulated Dataflow Computer
IEEE Transactions on Computers
Wavefront Array Processor: Language, Architecture, and Applications
IEEE Transactions on Computers
Pin Limitations and Partitioning of VLSI Interconnection Networks
IEEE Transactions on Computers
Measuring the Parallelism Available for Very Long Instruction Word Architectures
IEEE Transactions on Computers
Cooperating Reduction Machines
IEEE Transactions on Computers
Accurate branch prediction for short threads
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
A list-processing-oriented data flow machine architecture
AFIPS '82 Proceedings of the June 7-10, 1982, national computer conference
HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Efficient compilation for queue size constrained queue processors
Parallel Computing
Loop-Aware Instruction Scheduling with Dynamic Contention Tracking for Tiled Dataflow Architectures
CC '09 Proceedings of the 18th International Conference on Compiler Construction: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009
PLUG: flexible lookup modules for rapid deployment of new protocols in high-speed routers
Proceedings of the ACM SIGCOMM 2009 conference on Data communication
OptionStream: An automated system for tracking derivative effects on equity prices
Expert Systems with Applications: An International Journal
Bounded dataflow networks and latency-insensitive circuits
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
A task graph execution manager for reconfigurable multi-tasking systems
Microprocessors & Microsystems
Evaluating a low-power dual-core architecture
APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
Agent-oriented programming: from prolog to guarded definite clauses
Agent-oriented programming: from prolog to guarded definite clauses
WSEAS Transactions on Computers
Task superscalar: using processors as functional units
HotPar'10 Proceedings of the 2nd USENIX conference on Hot topics in parallelism
Task Superscalar: An Out-of-Order Task Pipeline
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
The C compiler generating a source file in VHDL for a dynamic dataflow machine
MMACTEE'09 Proceedings of the 11th WSEAS international conference on Mathematical methods and computational techniques in electrical engineering
Hardware budget and runtime system for data-driven multithreaded chip multiprocessor
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
An analysis of program execution on a recursive stream-oriented data flow architecture
Journal of Systems and Software
Xflow: declarative data processing for the web
Proceedings of the 17th International Conference on 3D Web Technology
OpenStream: Expressiveness and data-flow compilation of OpenMP streaming programs
ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers
Proceedings of the 18th International Conference on 3D Web Technology
Triggered instructions: a control paradigm for spatially-programmed architectures
Proceedings of the 40th Annual International Symposium on Computer Architecture
Turning nondeterminism into parallelism
Proceedings of the 2013 ACM SIGPLAN international conference on Object oriented programming systems languages & applications
Towards Generic Embedded Multiprocessing for RVC-CAL Dataflow Programs
Journal of Signal Processing Systems
| Hi-index | 0.04 |
A processor is described which can achieve highly parallel execution of programs represented in data-flow form. The language implemented incorporates conditional and iteration mechanisms, and the processor is a step toward a practical data-flow processor for a Fortran-level data-flow language. The processor has a unique architecture which avoids the problems of processor switching and memory/processor interconnecion that usually limit the degree of realizable concurrent processing. The architecture offers an unusual solution to the problem of structuring and managing a two-level memory system.