Content Addressable Parallel Processors
Content Addressable Parallel Processors
A preliminary architecture for a basic data-flow processor
ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
Modeling and simulating data flow computations at machine language level
SIGMETRICS '79 Proceedings of the 1979 ACM SIGMETRICS conference on Simulation, measurement and modeling of computer systems
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This paper presents a new data flow computer architecture using two types of memory: program memory and token memory. The program memory (PM) stores a data flow program or graph indicating data dependencies among instructions. The PM need not be changed during execution of one program and is duplicated for each processing or functional unit. The token memory (TM) stores mainly currently needed data values and plays a role similar to accumulators or registers in conventional computers. The size of the TM is expected to be relatively small because the data values occupy space in the TM for a very short time. The small scale TM in our architecture makes it possible to reduce the complexity of the switch mechanism between functional units and memories, and the size of the control circuit.