The warp computer: Architecture, implementation, and performance
IEEE Transactions on Computers
A benchmark package for sparse matrix computations
ICS '88 Proceedings of the 2nd international conference on Supercomputing
A preliminary architecture for a basic data-flow processor
ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
Loop based design for wafer scale systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The basics of task-flow architecture and the simulated wafer-scale implementation of flowing tasks (SWIFT), a register-transfer simulator that investigates the behavior of task-flow programs, are discussed. SWIFT simulates a ring of cells with two pipeline stages between successive cells. Each cell contains an arithmetic logic unit (ALU), a receive queue for holding incoming transmission packets, and a memory for storing memory packets (MPs). The chain wafer-scale integration (WSI) architecture that allows linear arrays to be configured from the working cells on a partially good wafer is applied to task-flow-machine implementations. Results from a limited Monte Carlo simulation run to predict yields for a 164-cell wafer configured using the chain WSI technique are presented. Results of a simulated sparse matrix-vector multiplication application of the task-flow architecture are also presented.