Loop based design for wafer scale systems

Authors:
R. V. Pelletier;R. D. McLeod
Affiliations:
Bell Northern Research, Ottawa, Ontario, Canada;Department of Electrical and Computer Engineering, University of Manitoba, Winnipeg, Manitoba, Canada
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
1994

Citing 4
Cited 0

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Abstract

This paper presents a loop based design scheme suitable for wafer scale systems and introduces a variant of the basic reconfiguration algorithm. The underlying topology has been extended to a nonplanar graph of vertex degree five. The yield for this system is higher than that of a planar graph of vertex degree six and requires less hardware for its implementation. Several comparisons among various topologies and reconfiguration algorithms are made within the context of percolation models.