A Survey of Microcellular Research
Journal of the ACM (JACM)
INFORMATION PROCESSING AND TRANSMISSION IN CELLULAR AUTOMATA
INFORMATION PROCESSING AND TRANSMISSION IN CELLULAR AUTOMATA
AUTOMATIC TEST, CONFIGURATION AND REPAIR OF CELLULAR ARRAYS
AUTOMATIC TEST, CONFIGURATION AND REPAIR OF CELLULAR ARRAYS
Programmable cellular logic arrays
Programmable cellular logic arrays
Cellular Automata
Theory of Self-Reproducing Automata
Theory of Self-Reproducing Automata
Combinational and Sequential Cellular Structures
IEEE Transactions on Computers
Testing for faults in combinational cellular logic arrays
FOCS '67 Proceedings of the 8th Annual Symposium on Switching and Automata Theory (SWAT 1967)
Acceptable Testing of VLSI Components Which Contain Error Correctors
IEEE Transactions on Computers
A Robust Matrix-Multiplication Array
IEEE Transactions on Computers
The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors
IEEE Transactions on Computers
The yield enhancement of field-programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Loop based design for wafer scale systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents an LSI-oriented approach to computer-maintained rectangular arrays of programmable logic. No signal line connects more than a few cells. A loading mechanism in each cell allows a computer directly connected to one cell to load any good cell that is not walled off by flawed cells. A loading arm is grown by programming cells to form a path that carries loading information. Cell mechanisms allow a computer to monitor the growth of a loading arm, and to change the arm's route or retract the arm to avoid faulty cells. Properly loaded cells carry test signals between a tested cell and a testing computer directly connected to only a few cells. The computer discovers the faulty cells in an array, and repairs the array by loading the array's good cells. This allows a computer to embed a perfect, very reliable digital machine on an entire flawed semiconductor wafer.