Systematic codes and their applications to computer systems.
Systematic codes and their applications to computer systems.
Orthogonal Latin Square Configuration for LSI Memory Yield and Reliability Enhancement
IEEE Transactions on Computers
An Approach to Highly Integrated, Computer-Maintained Cellular Arrays
IEEE Transactions on Computers
Coding for Random-Access Memories
IEEE Transactions on Computers
Synchronization and Matching in Redundant Systems
IEEE Transactions on Computers
Implementation of an Experimental Fault-Tolerant Memory System
IEEE Transactions on Computers
An Organization for a Highly Survivable Memory
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
A General Class of Maximal Codes ror Computer Applications
IEEE Transactions on Computers
IEEE Transactions on Computers
Coding techniques for failure recovery in a distributive modular memory organization
AFIPS '71 (Spring) Proceedings of the May 18-20, 1971, spring joint computer conference
A Reliability Model for Various Switch Designs in Hybrid Redundancy
IEEE Transactions on Computers
A class of optimal minimum odd-weight-column SEC-DED codes
IBM Journal of Research and Development
IBM Journal of Research and Development
An Algebraic Model of Fault-Masking Logic Circuits
IEEE Transactions on Computers
On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays
IEEE Transactions on Computers
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If a VLSI chip is partitioned into functional units (FU's) and redundant FU's are added, error correcting codes may be employed to increase the yield and/or reliability of the chip. Acceptable testing is defined to be testing the chip with the error corrector functioning, thus obtaining the maximum increase in yield afforded by the error correction. The acceptable testing theorem shows that the use of coding and error correction in conjunction with acceptable testing can significantly increase the yield of VLSI chips without seriously compromising their reliability.