Coding for Random-Access Memories

Authors:
J. J. Stiffler
Affiliations:
Raytheon Company
Venue:
IEEE Transactions on Computers
Year:
1978

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Abstract

A new decoding technique is presented for correcting errors due to bit-oriented hardware failures in parallel, random-access memories. It is shown that the resulting decoder compares favorably, both in complexity and in decoding delay, with currently implemented bit-switching techniques used for the same purpose.