A self-checking generalized prediction checker and its use for built-in testing
IEEE Transactions on Computers
IEEE Transactions on Computers
Decoding of DBEC-TBED Reed-Solomon codes
IEEE Transactions on Computers
Dynamic Memory Design for Low Data-Retention Power
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Constructions of the SbEC-DbED and DbEC codes, and their applications
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Two error-detecting and correcting circuits for space applications
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A Class of Optimal Fixed-Byte Error Protection Codes for Computer Systems
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Acceptable Testing of VLSI Components Which Contain Error Correctors
IEEE Transactions on Computers
Measurement and Generation of Error Correcting Codes for Package Failures
IEEE Transactions on Computers
Lookaside Techniques for Minimum Circuit Memory Translators
IEEE Transactions on Computers
Fault-Tolerant 256K Memory Designs
IEEE Transactions on Computers
A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems
IEEE Transactions on Computers
Coding for Random-Access Memories
IEEE Transactions on Computers
Implementation of an Experimental Fault-Tolerant Memory System
IEEE Transactions on Computers
Single Byte Error Correcting Double Byte Error Detecting Codes for Memory Systems
IEEE Transactions on Computers
SEC-DED Nonbinary Code for Fault-Tolerant Byte-Organized Memory Implemented with Quaternary Logic
IEEE Transactions on Computers
Erasure and Error Decoding for Semiconductor Memories
IEEE Transactions on Computers
Area Reliability Trade-Off in Improved Reed Muller Coding
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Architecture Design for Soft Errors
Architecture Design for Soft Errors
Design of parallel fault-secure encoders for systematic cyclic block transmission codes
Microelectronics Journal
Virtualized and flexible ECC for main memory
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
IVEC: off-chip memory integrity protection for both security and reliability
Proceedings of the 37th annual international symposium on Computer architecture
On the Duality of Probing and Fault Attacks
Journal of Electronic Testing: Theory and Applications
An adaptive code rate EDAC scheme for random access memory
Proceedings of the Conference on Design, Automation and Test in Europe
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
Design of Memories with Concurrent Error Detection and Correction by Nonlinear SEC-DED Codes
Journal of Electronic Testing: Theory and Applications
A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System Applications
IEEE Transactions on Computers
Review: A survey of memory error correcting techniques for improved reliability
Journal of Network and Computer Applications
Crosstalk-aware channel coding schemes for energy efficient and reliable NOC interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Matrix codes for reliable and cost efficient memory chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic generation of error control codes for computer applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fault Tolerant Single Error Correction Encoders
Journal of Electronic Testing: Theory and Applications
A self-checking hardware journal for a fault-tolerant processor architecture
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
MAGE: adaptive granularity and ECC for resilient and power efficient memory systems
SC '12 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
Memory array protection: check on read or check on write?
Proceedings of the Conference on Design, Automation and Test in Europe
Bit mapping for balanced PCM cell programming
Proceedings of the 40th Annual International Symposium on Computer Architecture
Hierarchical decoding of double error correcting codes for high speed reliable memories
Proceedings of the 50th Annual Design Automation Conference
Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Practical nonvolatile multilevel-cell phase change memory
SC '13 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
Rethinking algorithm-based fault tolerance with a cooperative software-hardware approach
SC '13 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
Journal of Electronic Testing: Theory and Applications
Implicit-storing and redundant-encoding-of-attribute information in error-correction-codes
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the International Conference on Computer-Aided Design
Soft error tolerant Content Addressable Memories (CAMs) using error detection codes and duplication
Microprocessors & Microsystems
| Hi-index | 0.04 |
The class of codes described in this paper is used for single-error correction and double-error detection (SEC-DED). It is equivalent to the Hamming SEC-DED code in the sense that for a specified number k of data bits, the same number of check bits r is used. The minimum odd-weight-column code is suitable for applications to computer memories or parallel systems. A computation indicates that this code is better in performance, cost and reliability than are conventional Hamming SEC-DED codes.