Fault-Tolerant 256K Memory Designs

• Authors: R. M. Tanner
• Venue: IEEE Transactions on Computers
• Year: 1984

A series of designs for a 256K memory are presented which integrate error-correcting coding into the memory organization. Starting from a simple single-error correcting product code, the successive designs explore trade-offs in coding efficiency, access delay, and complexity of communication and computation. In the most powerful design, all the 256K bits are organized so that they form a codeword in a double-error-correcting triple-error-detecting code derived from a projective plane. Because all of the bits are components of this single codeword, the coding efficiency is very high; the required parity check bits increase the storage by only 3 percent, approximately. Single error correction can take place at the time of a read with very little additional delay compared to that of a normal irredundant memory. Multiple error correction can be performed by the memory management system. A variety of failure modes, including failure of a whole column of one of the constituent 64 x 64 subarrays can be tolerated. Writing into the memory is somewhat slower than in a conventional memory, involving a read-write cycle.