Measurement and Generation of Error Correcting Codes for Package Failures
IEEE Transactions on Computers
A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems
IEEE Transactions on Computers
Code Constructions for Error Control in Byte Organized Memory Systems
IEEE Transactions on Computers
Single Byte Error Correcting Double Byte Error Detecting Codes for Memory Systems
IEEE Transactions on Computers
Error-Correcting Codes with Byte Error-Detection Capability
IEEE Transactions on Computers
SEC-DED Nonbinary Code for Fault-Tolerant Byte-Organized Memory Implemented with Quaternary Logic
IEEE Transactions on Computers
A class of optimal minimum odd-weight-column SEC-DED codes
IBM Journal of Research and Development
IBM Journal of Research and Development
Comments on the Decoding Algorithms of DBEC-TBED Reed-Solomon Codes
IEEE Transactions on Computers
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A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K bit DRAM's are organized in 32K - 8 bit-bytes. Byte-oriented codes such as Reed-Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. In this correspondence we present a special decoding technique for double-byte-error-correcting (DBEC), triple-byte-error-detecting (TBED) RS codes which is capable of high-speed operation. This technique is designed to find the error locations and the error values directly from the syndrome without having to use the iterative algorithm to find the error locator polynomial.