A class of optimal minimum odd-weight-column SEC-DED codes
IBM Journal of Research and Development
IBM Journal of Research and Development
Byte-Oriented Error-Correcting Codes for Semiconductor Memory Systems
IEEE Transactions on Computers
IEEE Transactions on Computers
Decoding of DBEC-TBED Reed-Solomon codes
IEEE Transactions on Computers
Constructions of the SbEC-DbED and DbEC codes, and their applications
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Symbol error correcting codes for memory applications
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Error-correcting codes for semiconductor memory applications: a state-of-the-art review
IBM Journal of Research and Development
A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System Applications
IEEE Transactions on Computers
Automatic generation of error control codes for computer applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
QoS-sensitive transport of real-time MPEG video using adaptive redundancy control
Computer Communications
On some new m-spotty Lee weight enumerators
Designs, Codes and Cryptography
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In a memory that uses byte-organized memory chips, each containing b (=2) output bits, a single chip failure is likely to affect many bits within a byte. Single byte error correcting-double byte error detecting codes (SbEC-DbED codes) are used in this kind of memory system to increase reliability.