A VLSI Design of a Pipeline Reed-Solomon Decoder
IEEE Transactions on Computers
Single Byte Error Correcting Double Byte Error Detecting Codes for Memory Systems
IEEE Transactions on Computers
A class of optimal minimum odd-weight-column SEC-DED codes
IBM Journal of Research and Development
CAA Decoder for Cellular Automata Based Byte Error Correcting Code
IEEE Transactions on Computers
A Systolic Power-Sum Circuit for GF(2/sup m/)
IEEE Transactions on Computers
Design of CAECC - Cellular Automata Based Error Correcting Code
IEEE Transactions on Computers
CA-Based Byte Error-Correcting Code
IEEE Transactions on Computers
| Hi-index | 14.99 |
In this paper, some efficient methods of solving equations over Galois field GF(2m) are proposed. Using these algorithms, decoders for triple-and quadruple-error-correcting Bose-Chaudhuri-Hocquenghem (BCH) codes are shown. More- over, we propose a new method of making high-speed decoders for double-error-correcting/triple-error-detecting BCH or Reed- Solomon (RS) codes by adding a simple error-identifying circuit to a decoder for double-error-correcting codes. By incorporating ROM's (read only memory) in a decoder, the complex logic circuits are eliminated and then we can easily construct a high- speed decoder. We evaluate the complexity of the decoders and show that each of them can be accommodated in a single chip LSI.