Group Properties of Cellular Automata and VLSI Applications
IEEE Transactions on Computers
IEEE Transactions on Computers
Error-control coding for computer systems
Error-control coding for computer systems
Cellular Automata-Based Signature Analysis for Built-In Self-Test
IEEE Transactions on Computers
Theory and Applications of Cellular Automata in Cryptography
IEEE Transactions on Computers
Design of CAECC - Cellular Automata Based Error Correcting Code
IEEE Transactions on Computers
CA-Based Byte Error-Correcting Code
IEEE Transactions on Computers
Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern Generator
IEEE Transactions on Computers
Parallel Decoder for Cellular Automata Based Byte Error Correcting Code
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A TCAD system for VLSI implementation of the CVD process using VHDL
Integration, the VLSI Journal
Image security system using recursive cellular automata substitution
Pattern Recognition
An Improved Double Byte Error Correcting Code Using Cellular Automata
ACRI '08 Proceedings of the 8th international conference on Cellular Automata for Reseach and Industry
Null boundary 90/150 cellular automata for multi-byte error correcting code
ACRI'10 Proceedings of the 9th international conference on Cellular automata for research and industry
| Hi-index | 14.98 |
Design of Cellular Automata (CA) based byte error correcting code analogous to extended Reed-Solomon code has been proposed in [1], [2]. This code has same restrictions on error correction as that of extended R-S code. In this paper a new design scheme has been reported for parallel implementation of CA based SbEC/DbED and DbEC/DbED code that is analogous to the conventional R-S code. Both the encoder and decoder of this code can be efficiently implemented with an array of CA (CAA) with high throughput. The design is ideally suited for high speed memory systems built with byte organized RAM chips. Extension of the scheme to detect/correct larger number of byte errors has also been reported. Throughput of the decoder to handle t byte errors (t驴 4) can be found to be substantially better than that of conventional R-S decoder. The proposed decoder provides a simple, modular and cost effective design that ideally suits for VLSI implementation.