Error-Control Coding in Computers
Computer
Fault-tolerance design of the IBM Enterprise System/9000 Type 9021 processors
IBM Journal of Research and Development
Comparison of Duplex and Triplex Memory Reliability
IEEE Transactions on Computers
A New Residue Arithmetic Error Correction Scheme
IEEE Transactions on Computers
On the Analysis and Design of Group Theoretical t-syEC/AUED Codes
IEEE Transactions on Computers
CAA Decoder for Cellular Automata Based Byte Error Correcting Code
IEEE Transactions on Computers
A Hyper Optimal Encoding Scheme for Self-Checking Circuits
IEEE Transactions on Computers
Nonprime Memory Systems and Error Correction in Address Translation
IEEE Transactions on Computers
A Class of Error Control Codes for Byte Organized Memory Systems -SbEC-(Sb+S)ED Codes-
IEEE Transactions on Computers
Signed Binary Addition Circuitry with Inherent Even Parity Outputs
IEEE Transactions on Computers
A Self-Testing Nonincreasing Order Checker
IEEE Transactions on Computers
Optimal Self-Testing Embedded Parity Checkers
IEEE Transactions on Computers
A New Design Method for Self-Checking Unidirectional Combinational Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
On-Line Error Detection for Bit-Serial Multipliers in GF(2m)
Journal of Electronic Testing: Theory and Applications
Optimal Two-Level Unequal Error Control Codes for Computer Systems
IEEE Transactions on Computers
Coding for High Availability of a Distributed-Parallel Storage System
IEEE Transactions on Parallel and Distributed Systems
Experimental Results for Self-Dual Multi-Output Combinational Circuits
Journal of Electronic Testing: Theory and Applications
Reliable low-power design in the presence of deep submicron noise (embedded tutorial session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
High-Speed Parallel-Prefix Modulo 2n - 1 Adders
IEEE Transactions on Computers - Special issue on computer arithmetic
Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic Codes
Journal of Electronic Testing: Theory and Applications
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Self-adjusting output data compression: an efficient BIST technique for RAMs
Proceedings of the conference on Design, automation and test in Europe
Medium access control for ATM-to-CDMA interface
Wireless Networks
Logic Complement, a New Method of Checking the Combinational Circuits
Automation and Remote Control
Synthesizing Fast, Online-Testable Control Units
IEEE Design & Test
Transient Fault Tolerance in Digital Systems
IEEE Micro
Byte Unidirectional Error Correcting and Detecting Codes
IEEE Transactions on Computers
Multibit Correcting Data Interface for Fault-Tolerant Systems
IEEE Transactions on Computers
Some Codes for Correcting and Detecting Unidirectional Byte Errors
IEEE Transactions on Computers
Berger Check Prediction for Array Multipliers and Array Dividers
IEEE Transactions on Computers
IEEE Transactions on Computers
Constant Weight Codes for Correcting Symmetric Errors and Detecting Unidirectional Errors
IEEE Transactions on Computers
Error Correcting Codes Over Z/sub 2(m/) for Algorithm-Based Fault Tolerance
IEEE Transactions on Computers
Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands
IEEE Transactions on Computers
Design of CAECC - Cellular Automata Based Error Correcting Code
IEEE Transactions on Computers
CA-Based Byte Error-Correcting Code
IEEE Transactions on Computers
Unidirectional Bit/Byte Error Control
IEEE Transactions on Computers
Construction of Systematic Codes for Unidirectional Error Control
IEEE Transactions on Computers
Efficient Online and Offline Testing of Embedded DRAMs
IEEE Transactions on Computers
Theory of Extended Linear Machines
IEEE Transactions on Computers
Grid Coverage for Surveillance and Target Location in Distributed Sensor Networks
IEEE Transactions on Computers
Cellular Automata Based Cryptosystem (CAC)
ICICS '02 Proceedings of the 4th International Conference on Information and Communications Security
Cellular Automata Based Authentication (CAA)
ACRI '01 Proceedings of the 5th International Conference on Cellular Automata for Research and Industry
Embedded self-testing checkers for low-cost arithmetic codes
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Fault-tolerant systems with concurrent error-locating capability
Journal of Computer Science and Technology
Generalized modular design of testable m-out-of-n code checker
ATS '95 Proceedings of the 4th Asian Test Symposium
Error Detection in Fault Secure Controllers using State Encoding
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Constructions of the SbEC-DbED and DbEC codes, and their applications
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Single fault masking logic designs with error correcting codes
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Symbol error correcting codes for memory applications
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Optimal two-level unequal error control codes for computer systems
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Approaches for a reliable high-performance distributed-parallel storage system
HPDC '96 Proceedings of the 5th IEEE International Symposium on High Performance Distributed Computing
VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Cryptosystem Designed for Embedded System Security
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Self-exercising self testing k-order comparators
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A linear code-preserving signature analyzer COPMISR
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
16.1 Novel Single and Double Output TSC Berger Code Checkers
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
14.1 Fast Self-Recovering Controllers
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Modular TSC Checkers for Bose-Lin and Bose Codes
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Error Detecting Refreshment for Embedded DRAMs
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Checking the Integrity of Trees
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
A Class of Optimal Fixed-Byte Error Protection Codes for Computer Systems
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Error Detection and Handling in a Superscalar, Speculative Out-of-Order Execution Processor System
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Error Correcting Strategy for High Speed and High Density Reliable Flash Memories
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Computers
Low-power MIMO signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Modulo 2n ± 1 Adder Design Using Select-Prefix Blocks
IEEE Transactions on Computers
A Class of M-Ary Asymmetric Symbol Error Correcting Codes for Data Entry Devices
IEEE Transactions on Computers
Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Codes
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Towards fault-tolerant cryptographic computations over finite fields
ACM Transactions on Embedded Computing Systems (TECS)
Parallel Decoding Cyclic Burst Error Correcting Codes
IEEE Transactions on Computers
Multiple-level concatenated coding in embryonics: a dependability analysis
GECCO '05 Proceedings of the 7th annual conference on Genetic and evolutionary computation
XPAND: An Efficient Test Stimulus Compression Technique
IEEE Transactions on Computers
Performance Models for Network Processor Design
IEEE Transactions on Parallel and Distributed Systems
Comments on "Carry checking/parity prediction adders and ALUs"
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design for dependability in emerging technologies
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Design of application-specific instructions and hardware accelerator for reed-solomon codecs
EURASIP Journal on Applied Signal Processing
On concurrent detection of errors in polynomial basis multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Check bit prediction using dong's code for logic functions
ISTASC'04 Proceedings of the 4th WSEAS International Conference on Systems Theory and Scientific Computation
A Non-linear Split Error Detection Code
Fundamenta Informaticae
Problems of Information Transmission
Aspects regarding the use of SEC-DED codes to the cache level of a memory hierarchy
AIKED'08 Proceedings of the 7th WSEAS International Conference on Artificial intelligence, knowledge engineering and data bases
Area Reliability Trade-Off in Improved Reed Muller Coding
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
An Improved Double Byte Error Correcting Code Using Cellular Automata
ACRI '08 Proceedings of the 8th international conference on Cellular Automata for Reseach and Industry
Fault-Tolerant Memory Design and Partitioning Issues in Embryonics
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
Power consumption of fault tolerant busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Montgomery exponent architecture based on programmable cellular automata
Mathematics and Computers in Simulation
Elliptic curve based hardware architecture using cellular automata
Mathematics and Computers in Simulation
A General Class of M-Spotty Byte Error Control Codes
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Instruction-Level Fault Tolerance Configurability
Journal of Signal Processing Systems
Nonconcurrent error correction in the presence of roundoff noise
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Design of parallel fault-secure encoders for systematic cyclic block transmission codes
Microelectronics Journal
A reconfigurable FEC system based on Reed-Solomon codec for DVB and 802.16 network
WSEAS Transactions on Circuits and Systems
A high-speed two-cell BCH decoder for error correcting in MLC NOR flash memories
IEEE Transactions on Circuits and Systems II: Express Briefs
Protective redundancy overhead reduction using instruction vulnerability factor
Proceedings of the 7th ACM international conference on Computing frontiers
Reducing cache power with low-cost, multi-bit error-correcting codes
Proceedings of the 37th annual international symposium on Computer architecture
A combinatorial approach to X-tolerant compaction circuits
IEEE Transactions on Information Theory
Fault tolerant techniques for reconfigurable platforms
Proceedings of the 1st Amrita ACM-W Celebration on Women in Computing in India
Design of Memories with Concurrent Error Detection and Correction by Nonlinear SEC-DED Codes
Journal of Electronic Testing: Theory and Applications
Determining all indecomposable codes over some Hopf algebras
Journal of Computational and Applied Mathematics
New degree computationless modified euclid algorithm and architecture for reed-solomon decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fault-tolerant permutation network modulo arithmetic processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic generation of error control codes for computer applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-efficient cache design using variable-strength error-correcting codes
Proceedings of the 38th annual international symposium on Computer architecture
System implications of memory reliability in exascale computing
Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis
Cellular automata architecture for elliptic curve cryptographic hardware
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part III
Modular divider for elliptic curve cryptographic hardware based on programmable CA
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part IV
High-speed architecture for three-parallel Reed-Solomon decoder using S-DCME
Proceedings of the 4th International Conference on Uniquitous Information Management and Communication
Three-Parallel Reed-Solomon Decoder Using S-DCME for High-Speed Communications
Journal of Signal Processing Systems
Evolutionary hardware architecture for division in elliptic curve cryptosystems over GF(2n)
ICNC'05 Proceedings of the First international conference on Advances in Natural Computation - Volume Part III
ACRI'06 Proceedings of the 7th international conference on Cellular Automata for Research and Industry
Error detection and correction in switched linear controllers via periodic and non-concurrent checks
Automatica (Journal of IFAC)
Constructions for binary codes correcting asymmetric errors from function fields
TAMC'12 Proceedings of the 9th Annual international conference on Theory and Applications of Models of Computation
A Non-linear Split Error Detection Code
Fundamenta Informaticae
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
New Cost-Effective Simplified Euclid's Algorithm for Reed-Solomon Decoders
Journal of Signal Processing Systems
Direct compare of information coded with error-correcting codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Techniques for compensating memory errors in JPEG2000
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploring DRAM organizations for energy-efficient and resilient exascale memories
SC '13 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
ACM Transactions on Architecture and Code Optimization (TACO)
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