Error-control coding for computer systems
Error-control coding for computer systems
IEEE Transactions on Computers
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
Fast Run-Time Fault Location in Dependable FPGA-Based Applications
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
A survey of fault tolerant methodologies for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An Adaptive Fault-Tolerant Memory System for FPGA-based Architectures in the Space Environment
AHS '07 Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems
Online fault tolerance for FPGA logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware Controlled and Software Independent Fault Tolerant FPGA Architecture
ADCOM '07 Proceedings of the 15th International Conference on Advanced Computing and Communications
A Novel Design Flow for the Performance Optimization of Fault Tolerant Circuits on SRAM-based FPGA's
AHS '08 Proceedings of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems
Fault tolerant system design and SEU injection based testing
Microprocessors & Microsystems
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Reconfigurable architectures possess the flexibility of software solutions as well as the high performance typified by hardware implementations to offer an excellent platform for developing quality-driven embedded applications. Among reconfigurable platforms, the dynamically Reconfigurable Field Programmable Gate Arrays (FPGAs) are most frequently employed for developing adaptive hardware software systems, so called Systems-on-Chip (SoC). For these systems to be fielded in harsh environments such as those encountered in space, extra-terrestrial locations and regions of extreme conditions on the earth, one must adopt fault tolerant design techniques to ensure uninterrupted and reliable operation despite the occurrence of faults. Commercial Off-the-Shelf (COTS) FPGA components offer a cost effective design trajectory where the designer can choose among a rich variety of FT approaches and techniques. Even though a large body of research has delved into the problem of fault tolerant design, there is a paucity of survey that indicates their applicability to FPGA-based SoC design. This paper attempts to categorize and compare the various FT techniques and discuss how they can work together to provide a synergetic approach for fault tolerant FPGA design.