Transient and Permanent Fault Diagnosis for FPGA-Based TMR Systems
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
On-line testing and recovery in TMR systems for real-time applications
Proceedings of the IEEE International Test Conference 2001
Designing fault tolerant systems into SRAM-based FPGAs
Proceedings of the 40th annual Design Automation Conference
Proven correct monitors from PSL specifications
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A survey of fault tolerant methodologies for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Dependable Design for FPGA Based on Duplex System and Reconfiguration
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
SEU mitigation for sram-based fpgas through dynamic partial reconfiguration
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A TMR Scheme for SEU Mitigation in Scan Flip-Flops
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
On-Line Self-Healing of Circuits Implemented on Reconfigurable FPGAs
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
Automata-based assertion-checker synthesis of PSL properties
ACM Transactions on Design Automation of Electronic Systems (TODAES)
TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
From the bitstream to the netlist
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Proceedings of the conference on Design, automation and test in Europe
Digital Systems Architectures Based on On-line Checkers
DSD '08 Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
Secure processing using dynamic partial reconfiguration
Proceedings of the 5th Annual Workshop on Cyber Security and Information Intelligence Research: Cyber Security and Information Intelligence Challenges and Strategies
Dynamic Partial Reconfiguration in Space Applications
AHS '09 Proceedings of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems
High Availability Fault Tolerant Architectures Implemented into FPGAs
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Fault tolerant techniques for reconfigurable platforms
Proceedings of the 1st Amrita ACM-W Celebration on Women in Computing in India
Fault Tolerance of Multiple Logic Faults in SRAM-Based FPGA Systems
DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
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The methodology for the design and testing of fault tolerant systems implemented into an FPGA platform with different types of diagnostic techniques is presented in this paper. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance features of the digital design implemented into the SRAM-based FPGA. The methodology includes detection and localization of a faulty module in the system and its repair and bringing the system back to the state in which it operates correctly. The automatic repair process of a faulty module is implemented by a partial dynamic reconfiguration driven by a generic controller inside the FPGA. The presented methodology was verified on the ML506 development board with Virtex5 FPGA for different types of RTL components. Fault tolerant systems developed by the presented methodology were tested by means of the newly developed SEU simulation framework. The framework is based on the SEU simulation through the JTAG interface and allows us to select the region of the FPGA where the SEU is placed. The simulator does not require any changes in the tested design and is fully independent of the functions in the FPGA. The external SEU generator into FPGA is implemented and its function is verified on an evaluation board ML506 for several types of fault tolerant architectures. The experimental results show the fault coverage and SEU occurrence causing faulty behavior of verified architectures.