Formal Methods in System Design
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Assertion-Based Design
A proof of correctness for the construction of property monitors
HLDVT '05 Proceedings of the High-Level Design Validation and Test Workshop, 2005. on Tenth IEEE International
From PSL to LTL: a formal validation in HOL
TPHOLs'05 Proceedings of the 18th international conference on Theorem Proving in Higher Order Logics
Automata-based assertion-checker synthesis of PSL properties
ACM Transactions on Design Automation of Electronic Systems (TODAES)
PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams
Journal of Electronic Testing: Theory and Applications
Validating assertion language rewrite rules and semantics with automated theorem provers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimized temporal monitors for SystemC
RV'10 Proceedings of the First international conference on Runtime verification
Abstract property language for MDG model checking methodology
International Journal of Computer Applications in Technology
Optimized temporal monitors for SystemC
Formal Methods in System Design
Fault tolerant system design and SEU injection based testing
Microprocessors & Microsystems
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We developed an original method to synthesize monitors from declarative specifications written in the PSL standard. Monitors observe sequences of values on their input signals, and check their conformance to a specified temporal expression. Our method implements both the weak and strong versions of PSL FL operators, and has been proven correct using the PVS theorem prover. This paper discusses the salient aspects of the proof of our prototype implementation for on-line design verification